公开(公告)号：US20090265443A1

公开(公告)日：2009-10-22

申请号：US12139696

申请日：2008-06-16

申请人： Hirotaka Moribe ,  Shoji Kodama ,  Yasushi Nagai

发明人： Hirotaka Moribe ,  Shoji Kodama ,  Yasushi Nagai

IPC分类号： G06F15/16

CPC分类号： H04L12/2809 ,  G06F15/16 ,  H04L12/2807 ,  H04L12/2812 ,  H04L12/2834 ,  H04L12/2838 ,  H04L12/4625 ,  H04L67/1097

摘要： This network apparatus includes a confirmation unit for confirming an appliance connected to a network in a certain area at predetermined time intervals, a transfer unit for transferring a content retained in the appliance from the appliance connected to the network to a storage apparatus outside of the area, a setting unit for setting a virtual device of the appliance when the confirmation unit detects that the appliance has been disconnected from the network, and a distribution unit for distributing, when an acquisition request of the content is issued to the appliance disconnected from the network, the content read from the storage to a sending source of the acquisition request with the virtual device as the transmission source of the content.

摘要翻译： 该网络装置包括用于以预定的时间间隔确认连接到特定区域中的网络的设备的确认单元，用于将保存在设备中的内容从连接到网络的设备传送到区域外的存储设备的传送单元 设置单元，用于当所述确认单元检测到所述设备已经从所述网络断开连接时，设置所述设备的虚拟设备;以及分发单元，用于当将所述内容的获取请求发布到从所述网络断开连接的设备时， 将内容从存储器读取到采集请求的发送源，虚拟设备作为内容的传输源。

公开(公告)号：US20090222798A1

公开(公告)日：2009-09-03

申请号：US12332397

申请日：2008-12-11

申请人： Shinya IGUCHI ,  Takatoshi Kato ,  Masaya Umemura ,  Nobuaki Kohinata ,  Yasushi Nagai ,  Hiroshi Nakagoe ,  Keitaro Okasaki ,  Hirotaka Moribe ,  Takeshi Asahi

发明人： Shinya IGUCHI ,  Takatoshi Kato ,  Masaya Umemura ,  Nobuaki Kohinata ,  Yasushi Nagai ,  Hiroshi Nakagoe ,  Keitaro Okasaki ,  Hirotaka Moribe ,  Takeshi Asahi

IPC分类号： G06F9/45

CPC分类号： G06F8/52

摘要： A mobile device includes a memory for storing therein a subroutine management table to manage kinds of existing codes out of native code, first code and second code for a plurality of subroutines contained in content, a virtual machine, a precompile circuit for producing second code from first code and a subroutine management circuit for changing over processing in accordance with the kind of existing code for subroutine called up during execution of content. The subroutine management circuit judges kind of existing code with reference to the subroutine management table when the processing is changed over.

摘要翻译： 移动设备包括一个存储器，用于在其中存储子程序管理表以管理内容中的现有代码的种类，用于内容中包含的多个子程序的第一代码和第二代码，虚拟机，用于从第 第一代码和子程序管理电路，用于根据在执行内容期间调用的子程序的现有代码的种类来改变处理。 当处理转换时，子程序管理电路参考子程序管理表来判断现有代码的种类。

公开(公告)号：US20120210133A1

公开(公告)日：2012-08-16

申请号：US13456630

申请日：2012-04-26

申请人： Yasushi Nagai ,  Hiroshi Nakagoe ,  Shigeki Taira

发明人： Yasushi Nagai ,  Hiroshi Nakagoe ,  Shigeki Taira

IPC分类号： H04L9/32

CPC分类号： G06F21/72 ,  H04L9/0643 ,  H04L63/0485 ,  H04L63/123 ,  H04L63/166 ,  H04L2209/125

摘要： In the configuration performing a data processing by a hardware processing circuit (accelerator), to provide a technology capable of improving a poorness of processing efficiency by multiple accesses to the data, the following solving means are provided. A network data processing accelerator of the present network data processing apparatus comprises processing units corresponding to each processing of an encryption/decryption, a message authentication, and a checksum, and in the data processing including a combination of each processing, accesses for the same data of the memory and the like through a bus I/F unit and the like is collected together into one time, and a pipeline processing is performed using the least common multiple of the data processing unit of each processing.

摘要翻译： 在通过硬件处理电路（加速器）执行数据处理的配置中，为了提供能够通过多次访问数据来改善处理效率差的技术，提供了以下解决方案。 本网络数据处理装置的网络数据处理加速器包括对应于加密/解密，消息认证和校验和的每个处理的处理单元，并且在包括每个处理的组合的数据处理中，对相同数据的访问 通过总线I / F单元等将存储器等等一起收集在一起，并且使用每个处理的数据处理单元的最小公倍数来执行流水线处理。

公开(公告)号：US08181024B2

公开(公告)日：2012-05-15

申请号：US11779309

申请日：2007-07-18

申请人： Yasushi Nagai ,  Hiroshi Nakagoe ,  Shigeki Taira

发明人： Yasushi Nagai ,  Hiroshi Nakagoe ,  Shigeki Taira

IPC分类号： H04L9/32

CPC分类号： G06F21/72 ,  H04L9/0643 ,  H04L63/0485 ,  H04L63/123 ,  H04L63/166 ,  H04L2209/125

摘要： In the configuration performing a data processing by a hardware processing circuit (accelerator), to provide a technology capable of improving a poorness of processing efficiency by multiple accesses to the data, the following solving means are provided. A network data processing accelerator of the present network data processing apparatus comprises processing units corresponding to each processing of an encryption/decryption, a message authentication, and a checksum, and in the data processing including a combination of each processing, accesses for the same data of the memory and the like through a bus I/F unit and the like is collected together into one time, and a pipeline processing is performed using the least common multiple of the data processing unit of each processing.

摘要翻译： 在通过硬件处理电路（加速器）执行数据处理的配置中，为了提供能够通过多次访问数据来改善处理效率差的技术，提供了以下解决方案。 本网络数据处理装置的网络数据处理加速器包括对应于加密/解密，消息认证和校验和的每个处理的处理单元，并且在包括每个处理的组合的数据处理中，对相同数据的访问 通过总线I / F单元等将存储器等等一起收集在一起，并且使用每个处理的数据处理单元的最小公倍数来执行流水线处理。

公开(公告)号：US20090119355A1

公开(公告)日：2009-05-07

申请号：US12025891

申请日：2008-02-05

申请人： Hiroshi NAKAGOE ,  Yasushi Nagai

发明人： Hiroshi NAKAGOE ,  Yasushi Nagai

IPC分类号： G06F7/00

CPC分类号： G11B20/00086 ,  G06F7/00 ,  G11B20/0021 ,  G11B20/1833 ,  G11B2020/1843 ,  G11B2220/2516 ,  H04L9/0631 ,  H04L2209/122 ,  H04L2209/125 ,  H04L2209/34

摘要： This arithmetic logical unit outputs data to be used in checking the final result of an AES unit that encrypts a plain text block into an encrypted text block based on AES operation, and includes an arithmetic unit for computing parity data created based on XOR operation from an encryption key to be used as a key during AES encryption, parity data created based on XOR operation from a plain text block, and an AES operation halfway result output from the AES unit, and outputting a value that is equivalent to parity data created based on XOR operation from the final result of the AES unit.

摘要翻译： 该算术逻辑单元输出用于将基于AES操作将加密文本块加密的AES单元的最终结果的数据输出到加密文本块中，并且包括用于计算从基于AES操作的异或运算创建的奇偶校验数据的运算单元 在AES加密期间用作密钥的加密密钥，基于来自纯文本块的异或操作创建的奇偶校验数据，以及AES单元输出的AES操作中途结果，并输出等价于基于 来自AES单元的最终结果的异或运算。

公开(公告)号：US20080215769A1

公开(公告)日：2008-09-04

申请号：US11984432

申请日：2007-11-16

申请人： Hiroshi Nakagoe ,  Yasushi Nagai

发明人： Hiroshi Nakagoe ,  Yasushi Nagai

IPC分类号： G06F13/28

CPC分类号： H04L1/0052 ,  H04L1/0057

摘要： An operational circuit for performing an operation of an arbitrary number of input data pieces by using a DMA transfer according to a descriptor control and output results. The arbitrary number of input data pieces are divided into a plurality of pieces to perform an operation processing without performing the operation of the arbitrary number of input data pieces at a time. The operational circuit once stores an intermediate result for each of the divided operations in an external storage device, performs an operation processing read with an intermediate result in the next operation processing, and obtains a final result by repeating these operation processings. The operation is performed at a cyclic unit of processing corresponding to the number of address registers provided in the operational circuit.

摘要翻译： 一种操作电路，用于通过使用根据描述符控制和输出结果的DMA传输来执行任意数量的输入数据的操作。 任意数量的输入数据被分成多个，以执行一次操作处理，而不一次执行任意数量的输入数据的操作。 运算电路一次将分割运算的中间结果存储在外部存储装置中，进行下一个运算处理中的中间结果的运算处理，通过重复这些运算处理，得到最终结果。 该操作以对应于在操作电路中提供的地址寄存器的数量的循环处理单元进行。

公开(公告)号：US06994102B2

公开(公告)日：2006-02-07

申请号：US10695653

申请日：2003-10-29

申请人： Kunihiro Yamaguchi ,  Koichi Tamura ,  Akinori Araki ,  Yasushi Nagai

发明人： Kunihiro Yamaguchi ,  Koichi Tamura ,  Akinori Araki ,  Yasushi Nagai

IPC分类号： G05D11/00

CPC分类号： F16H61/0021 ,  F16H2061/0253 ,  G05D16/103 ,  Y10T137/2605 ,  Y10T137/2632 ,  Y10T137/7736 ,  Y10T137/7737 ,  Y10T477/6939

摘要： A pressure regulating valve which is comprised of a valve body being comprised of a cylinder, a spool slidably disposed in the cylinder with a clearance, the spool and the cylinder defining a pressure chamber and a space portion, and an urging member which urges the spool in a direction opposite to a direction of a force applied to the spool by fluid pressure in the pressure chamber. A supply passage fluidly communicates the cylinder and a fluid pressure supply source, and a drain passage fluidly communicates the cylinder and a sump. A through-passage formed in the spool fluidly communicates the pressure chamber and the space portion. An orifice disposed between the space portion and a sump limits a flow rate of fluid drained from the space portion to the sump. The spool is made of material having a lower thermal expansion coefficient than material of the valve body.

摘要翻译： 一种压力调节阀，由阀体构成，阀体由气缸构成，可滑动地设置在气缸中的阀芯间隙，阀芯和气缸限定压力室和空间部分，以及推动构件，其推动阀芯 在与压力室中的流体压力施加到阀芯的力的方向相反的方向上。 供给通道使气缸和流体压力供给源流体连通，排水通路将气缸与油槽流体连通。 形成在阀芯中的通路与压力室和空间部分流体连通。 设置在空间部分和贮槽之间的孔限制了从空间部分排出到贮槽的流体的流速。 阀芯由具有比阀体材料低的热膨胀系数的材料制成。

公开(公告)号：US06685588B2

公开(公告)日：2004-02-03

申请号：US10137054

申请日：2002-05-01

申请人： Katsuo Doi ,  Yasushi Nagai ,  Seiji Kitagawa

发明人： Katsuo Doi ,  Yasushi Nagai ,  Seiji Kitagawa

IPC分类号： F16G1302

CPC分类号： F16G13/06 ,  F16C19/26 ,  F16C33/34 ,  F16C33/6696

摘要： In a roller chain in which a plurality of rolling bodies is disposed between a roller and a bushing, between a bushing and a pin, or between a roller and a pin, the rolling bodies include at least one carbon-impregnated ceramic rolling body, or at least one carbon-coated steel rolling body. Preferably, the carbon-impregnated or carbon-coated rolling bodies are disposed in an alternating configuration with steel rolling bodies.

摘要翻译： 在滚子链中，多个滚动体设置在滚筒和衬套之间，衬套和销之间，或辊与销之间，滚动体包括至少一个碳浸陶瓷滚动体，或 至少一个碳涂层钢滚动体。 优选地，碳浸渍或碳涂覆的滚动体以与钢滚动体交替的形式设置。

公开(公告)号：US09092288B2

公开(公告)日：2015-07-28

申请号：US13290380

申请日：2011-11-07

申请人： Yasushi Nagai ,  Atsushi Shimizu ,  Hiroyuki Kasuya ,  Shoichi Akutsu ,  Shinji Kawamura ,  Yoshitaka Sumitomo

发明人： Yasushi Nagai ,  Atsushi Shimizu ,  Hiroyuki Kasuya ,  Shoichi Akutsu ,  Shinji Kawamura ,  Yoshitaka Sumitomo

IPC分类号： G06F9/44 ,  G06F7/00 ,  G06F11/30 ,  G07C5/00 ,  G06F9/445 ,  G06F11/14 ,  G06F1/30

CPC分类号： G06F8/61 ,  G06F1/30 ,  G06F11/1433 ,  G07C5/00

摘要： When a power supply is cut off on updating programs, improper data remains since the power source to be supplied to the vehicle-mounted device is unstable. The check for the improper data and restoration processing are required for a reactivation processing implemented by an update processing unit so that the update is completed correctly, therefore, the user is waited. In contrast, the update processing also implemented by the update processing unit for a time period during which the power source becomes unstable is interrupted, and implemented for the time period during which the power source voltage is stable. The power source voltage is considered to be unstable based on a function of the vehicle speed, brake pedal actuation, parking brake actuation, and/or power source activation. In consequence, the update processing is carried on steadily without making the user wait.

摘要翻译： 当电源更新程序被切断时，由于提供给车载设备的电源不稳定，所以不正确的数据仍然存在。 对于由更新处理单元执行的重新激活处理，需要检查不正确的数据和恢复处理，使得更新被正确完成，因此等待用户。 相反，在电源变得不稳定的时间段期间，由更新处理单元也实现的更新处理被中断，并且在电源电压稳定的时间段内实现。 基于车速，制动踏板驱动，驻车制动器致动和/或电源激活的功能，电源电压被认为是不稳定的。 因此，更新处理在不使用户等待的情况下稳定地进行。

公开(公告)号：US08176221B2

公开(公告)日：2012-05-08

申请号：US12595381

申请日：2008-03-21

申请人： Yasushi Nagai ,  Hiroshi Nakagoe ,  Shigeki Taira

发明人： Yasushi Nagai ,  Hiroshi Nakagoe ,  Shigeki Taira

IPC分类号： G06F13/28 ,  G06F13/00

CPC分类号： G06F13/28 ,  Y02D10/14

摘要： A DMA controller achieving real-time control of a DMA transfer relating to periodically operated peripheral devices at a low cost and with low power consumption. A typical embodiment of the invention is a DMA controller having: a counter for counting time; a counter comparator comparing a value of the counter and a counter value indicating an expected time of a DMA transfer; a peripheral device read unit reading a register of the peripheral device to acquire a state of a peripheral device by; and a state comparator comparing a value of the register read by the peripheral device read unit and a start condition of the DMA transfer, in which, with being triggered by establishment of a comparison result by the counter comparator, in accordance with a specified order, a processing of updating the counter value indicating the expected time of a DMA transfer to a value indicating a next expected time, a read of the register of the peripheral device by the peripheral device read unit, a comparison by the state comparator, and a DMA transfer on the condition that the comparison result by the state comparator is established are executed.

摘要翻译： DMA控制器以低成本和低功耗实现与周期性操作的外围设备相关的DMA传输的实时控制。 本发明的典型实施例是一种DMA控制器，具有：计数时间的计数器; 比较计数器的值和表示DMA传送的预期时间的计数器值的计数器比较器; 外围设备读取单元，读取外围设备的寄存器，以通过以下方式获取外围设备的状态; 以及状态比较器，比较由外围设备读取单元读取的寄存器的值和DMA传输的开始条件，其中，通过由计数器比较器建立比较结果而触发，根据指定的顺序， 将指示DMA传输的预期时间的计数器值更新为指示下一个预期时间的值的处理，外围设备读取单元对外围设备的寄存器的读取，状态比较器的比较以及DMA 在状态比较器的比较结果建立的条件下进行转移。