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1.发明授权
公开(公告)号：US5396297A
公开(公告)日：1995-03-07
申请号：US194695
申请日：1994-02-10
CPC分类号： H04N5/44504
摘要： Control data indicating the vertical start positions of display characters is written into the locations of a video RAM determined by a common column address and a plurality of column addresses. In each horizontal synchronizing period, all control data is read in sequence from the video RAM and set in sequence in a vertical start position register. A match is found between the contents of the vertical position counter indicating the current vertical position and the contents of the vertical start position register. When they match, after the horizontal synchronizing period, the video RAM is accessed with the control data as the vertical position start address.
摘要翻译： 指示显示字符的垂直开始位置的控制数据被写入由公共列地址和多个列地址确定的视频RAM的位置。 在每个水平同步周期中，从视频RAM依次读取所有控制数据，并依次设置在垂直起始位置寄存器中。 在垂直位置计数器的内容之间找到表示当前垂直位置和垂直起始位置寄存器的内容的匹配。 当它们匹配时，在水平同步周期之后，以控制数据作为垂直位置起始地址访问视频RAM。
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公开(公告)号：US20070067374A1
公开(公告)日：2007-03-22
申请号：US11275874
申请日：2006-02-01
IPC分类号： G06F7/58
CPC分类号： G06F7/588 , H04L9/06 , H04L9/0861
摘要： A random number generating circuit comprises a pseudo random number generating circuit that generates pseudo random numbers of an M-sequence; a physical random number generating circuit that generates physical random numbers; and a modulation circuit that modulates the physical random numbers generated by the physical random number generating circuit with the use of the pseudo random numbers generated by the pseudo random number generating circuit. The pseudo random number generating circuit can generate pseudo random numbers of a plurality of the M-sequences, and switches the M-sequences generated by the pseudo random number generating circuit based on the physical random numbers generated by the physical random number generating circuit.
摘要翻译： 一个随机数产生电路包括产生M序列的伪随机数的伪随机数产生电路; 产生物理随机数的物理随机数产生电路; 以及调制电路，其通过使用由伪随机数产生电路产生的伪随机数来调制由物理随机数产生电路产生的物理随机数。 伪随机数发生电路可以生成多个M序列的伪随机数，并且基于由物理随机数产生电路产生的物理随机数来切换由伪随机数产生电路产生的M序列。
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公开(公告)号：US06507884B1
公开(公告)日：2003-01-14
申请号：US09218768
申请日：1998-12-22
IPC分类号： G06F1200
CPC分类号： G06F12/06 , G06F12/04 , G11C16/102
摘要： A selection circuit causes either a memory 6H or 6L to enter an enabled state according to address data A16 of address data A0-A16 when a mode signal M is 1. The selection circuit comprises OR gates (10, 12) which output different outputs. When the address data A16 is 0, a nonvolatile memory 6L enters an enabled state. Then, the memory 6L is addressed according to the address data A0-A15 so that, for example, 8-bit lower data is written therein. On the other hand, when the address data A16 is 1, a nonvolatile memory 6H becomes in an enabled state. Then, the memory 6H is addressed according to the address data A0-A15 so that, for example, 8-bit upper data is written therein. Also, when an external terminal (17) is grounded, and a mode signal become 0, the OR gates (10, 12) outputs signals 0, so that the memories 6H, 6L simultaneously become in an enabled state. When data is read from corresponding addresses of each memory, data of, for example, 16-bits is obtained.
摘要翻译： 当模式信号M为1时，选择电路使得存储器6H或6L根据地址数据A0-A16的地址数据A16进入使能状态。选择电路包括输出不同输出的或门（10,12）。 当地址数据A16为0时，非易失性存储器6L进入使能状态。 然后，根据地址数据A0-A15对存储器6L进行寻址，以便例如在其中写入8位较低的数据。 另一方面，当地址数据A16为1时，非易失性存储器6H变为使能状态。 然后，根据地址数据A0-A15对存储器6H进行寻址，使得例如在其中写入8位上位数据。 此外，当外部端子（17）接地并且模式信号变为0时，或门（10,12）输出信号0，使得存储器6H，6L同时变为使能状态。 当从每个存储器的相应地址读取数据时，获得例如16位的数据。
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公开(公告)号：US20060171532A1
公开(公告)日：2006-08-03
申请号：US11275880
申请日：2006-02-01
IPC分类号： H04L9/28
CPC分类号： H04L9/0625 , H04L2209/125
摘要： An encryption processing circuit which performs a permutation process of a common key block encryption system that permutes input data of plural bits according to a per-bit correspondence rule and outputs the processed data. The encryption processing circuit comprises a data input unit that receives the input data of plural bits, the data input unit having an output port that outputs the received input data of plural bits in parallel; a data output unit that has an input port to which data of plural bits is input in parallel, the data output unit outputting the data of plural bits inputted to the input port; and a permuting unit that connects the output port and the input port according to the per-bit correspondence rule.
摘要翻译： 一种加密处理电路，其执行公共密钥块加密系统的置换处理，该公共密钥块加密系统根据每比特对应规则对多个比特的输入数据进行排列，并输出经处理的数据。 加密处理电路包括接收多个比特的输入数据的数据输入单元，数据输入单元具有输出端口，并行输出多个比特的接收输入数据; 数据输出单元，其输入并行输入多位的数据的输入端口，所述数据输出单元输出输入到所述输入端口的多位数据; 以及根据每位对应规则连接输出端口和输入端口的置换单元。
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公开(公告)号：US20060087403A1
公开(公告)日：2006-04-27
申请号：US11255244
申请日：2005-10-20
IPC分类号： H04L9/32
CPC分类号： G07C9/00309
摘要： A keyless entry system comprising a transmitter and a receiver. The transmitter increases a first number stored in the volatile memory according to rules, and transmits the first number by radio. The receiver receives the first number, and if the first number is greater than a second number stored in a memory, outputs a signal to indicate being authenticated as correct and updates the second number to the first number. Further, each time increase in the first number becomes a multiple of a predetermined number, the transmitter writes into a non-volatile memory a third number equal to the predetermined number plus the first number. When the first number in the volatile memory is erased due to the exchange, etc., of the battery, the transmitter reads out the third number from the non-volatile memory and writes the third number as the first number into the volatile memory.
摘要翻译： 一种无钥匙进入系统，包括发射机和接收机。 发射机根据规则增加存储在易失性存储器中的第一号码，并通过无线电发送第一号码。 接收器接收第一号码，并且如果第一号码大于存储在存储器中的第二号码，则输出指示正确认证的信号并将第二号码更新为第一号码。 此外，每当第一个数量的每次增加变为预定数量的倍数时，发送器将等于预定数量加上第一个数字的第三个数量写入非易失性存储器。 当由于电池的交换等而使易失性存储器中的第一个数字被擦除时，发送器从非易失性存储器读出第三个数字，并将第三个数字作为第一个数字写入到易失性存储器中。
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6.发明授权公开(公告)号：US06298412B1
公开(公告)日：2001-10-02
申请号：US09218944
申请日：1998-12-22
IPC分类号： G06F1202
CPC分类号： G06F15/7814 , G11C16/102
摘要： When writing of data into nonvolatile memories 8H and 8L is started, data D7 and D15 corresponding to the 128th word of a data input section 8B are inverted and outputted. When accurate writing is subsequently performed, the data D7 and D15 are outputted as they are. By monitoring a change of the data D7 and D15 from the nonvolatile memories 8H and 8L, it is possible to detect whether writing is still continuing or has already completed. Thus, by using nonvolatile memories of 8 bit data width or the like, a 16-bit microcomputer can be easily realized.
摘要翻译： 当将数据写入非易失性存储器8H和8L时，与数据输入部分8B的第128个字对应的数据D7和D15被反相输出。 当随后执行精确写入时，数据D7和D15原样输出。 通过监视来自非易失性存储器8H和8L的数据D7和D15的变化，可以检测写入是否仍在继续或已经完成。 因此，通过使用8位数据宽度等的非易失性存储器，可以容易地实现16位微型计算机。
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公开(公告)号：US4949052A
公开(公告)日：1990-08-14
申请号：US324284
申请日：1989-03-15
申请人： Kazumasa Chigira
发明人： Kazumasa Chigira
CPC分类号： G06F11/1604 , G06F11/20
摘要： A clock signal generator comprising a first oscillator which normally supplies clock pulses to the output of the clock signal generator, a first counter for counting the pulses generated from the first oscillator and producing a carry signal after counting n1 pulses generated from the first oscillator, a second oscillator for producing clock pulses for possible back-up purpose, a second counter for counting the pulses generated from the second oscillator and adapted to produce a carry signal after counting n2 pulses generated from the second oscillator and to be reset by the carry signal from the first counter, n2 being larger than n1, and a control circuit which blocks the output from the second oscillator as long as no carry signal is supplied thereto from the second oscillator. Therefore, should the first oscillator fail to produce period pulses, the second counter is not reset any more and the control circuit stops blocking the pulses from the second oscillator and forwards them to the output of the clock signal generator. Thus, the clock signal generator can continue to supply clock pulses even when one of its oscillators should fail to operate properly, and the reliability of the clock signal generator is improved.
摘要翻译： 一种时钟信号发生器，包括通常向时钟信号发生器的输出提供时钟脉冲的第一振荡器，用于对从第一振荡器产生的脉冲进行计数并在对从第一振荡器产生的n1个脉冲进行计数之后产生进位信号的第一计数器， 用于产生用于可能的备份目的的时钟脉冲的第二振荡器，用于对从第二振荡器产生的脉冲进行计数的第二计数器，用于在从第二振荡器产生的n2个脉冲计数之后产生进位信号，并由进位信号 第一计数器n2大于n1，并且只要没有从第二振荡器提供进位信号，就阻止来自第二振荡器的输出的控制电路。 因此，如果第一振荡器不能产生周期脉冲，则第二计数器不再复位，并且控制电路停止阻止来自第二振荡器的脉冲并将其转发到时钟信号发生器的输出。 因此，即使当其振荡器之一不能正常工作时，时钟信号发生器也可以继续提供时钟脉冲，并且改善了时钟信号发生器的可靠性。
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