公开(公告)号：US07249295B2

公开(公告)日：2007-07-24

申请号：US10400452

申请日：2003-03-28

申请人： Hiroyuki Fukuyama ,  Takeru Yonaga ,  Hitoshi Tanaka

发明人： Hiroyuki Fukuyama ,  Takeru Yonaga ,  Hitoshi Tanaka

IPC分类号： G11C29/00 ,  G11C7/00

CPC分类号： G11C29/30 ,  G11C2029/0405 ,  G11C2029/3202

摘要： A semiconductor test circuit including an input terminal, a controller, a setting circuit, a command generator, a transmission path switching circuit and a comparator. The input terminal receives serial data including a command code and control data. The controller receives a control signal from the input terminal and outputs an internal control signal. The setting circuit receives serial data from the input terminal and outputs it to the command generator in response to the internal control signal. The command generator then generates an interface signal based on this serial data. The switching circuit receives the signal from one of its ports and outputs the received signal to another port in response to the internal control signal and the command code, and the comparator compares the interface signal received from the command generator with the signal received from the switching circuit.

摘要翻译： 包括输入端子，控制器，设定电路，命令发生器，传输路径切换电路和比较器的半导体测试电路。 输入端子接收包括命令码和控制数据的串行数据。 控制器从输入端接收控制信号并输出​​内部控制信号。 设置电路从输入端接收串行数据，并根据内部控制信号将其输出到命令发生器。 然后，命令生成器基于该串行数据生成接口信号。 开关电路从其一个端口接收信号，并响应于内部控制信号和命令码将接收到的信号输出到另一端口，并且比较器将从命令发生器接收的接口信号与从切换接收的信号进行比较 电路。

公开(公告)号：US20050105348A1

公开(公告)日：2005-05-19

申请号：US10958658

申请日：2004-10-06

申请人： Hitoshi Tanaka ,  Hiroyuki Fukuyama ,  Takeru Yonaga

发明人： Hitoshi Tanaka ,  Hiroyuki Fukuyama ,  Takeru Yonaga

IPC分类号： G06F1/24 ,  G11C7/00

CPC分类号： G06F1/24

摘要： A reset circuit, which generates a reset signal for initializing an internal circuit of an integrated circuit device having an auto-loading function, includes a first register which stores a predetermined expected value data; a second register holding data which was auto-loaded; and a data comparison circuit which performs a comparison between the data held in the second register and the expected value data stored in the first register, and generates the reset signal based on a result of the comparison.

摘要翻译： 产生用于初始化具有自动加载功能的集成电路装置的内部电路的复位信号的复位电路包括存储预定期望值数据的第一寄存器; 第二个寄存器保存自动加载的数据; 以及数据比较电路，其执行保持在第二寄存器中的数据与存储在第一寄存器中的期望值数据之间的比较，并且基于比较的结果生成复位信号。

公开(公告)号：US07333372B2

公开(公告)日：2008-02-19

申请号：US10958658

申请日：2004-10-06

申请人： Hitoshi Tanaka ,  Hiroyuki Fukuyama ,  Takeru Yonaga

发明人： Hitoshi Tanaka ,  Hiroyuki Fukuyama ,  Takeru Yonaga

IPC分类号： G11C7/00

CPC分类号： G06F1/24

摘要： A reset circuit, which generates a reset signal for initializing an internal circuit of an integrated circuit device having an auto-loading function, includes a first register which stores a predetermined expected value data; a second register holding data which was auto-loaded; and a data comparison circuit which performs a comparison between the data held in the second register and the expected value data stored in the first register, and generates the reset signal based on a result of the comparison.

摘要翻译： 产生用于初始化具有自动加载功能的集成电路装置的内部电路的复位信号的复位电路包括存储预定期望值数据的第一寄存器; 第二个寄存器保存自动加载的数据; 以及数据比较电路，其执行保持在第二寄存器中的数据与存储在第一寄存器中的期望值数据之间的比较，并且基于比较的结果生成复位信号。

公开(公告)号：US07114113B2

公开(公告)日：2006-09-26

申请号：US10647378

申请日：2003-08-26

申请人： Takeru Yonaga ,  Hiroyuki Fukuyama ,  Hitoshi Tanaka

发明人： Takeru Yonaga ,  Hiroyuki Fukuyama ,  Hitoshi Tanaka

IPC分类号： G06F11/00

CPC分类号： G01R31/31725 ,  G01R31/31723 ,  G01R31/3187 ,  G01R31/31921 ,  G01R31/31926

摘要： A test circuit includes an input circuit for inputting data to select a test mode relative to a circuit to be tested and outputting result of selection of the test mode in synchronization with a first clock, a pattern generation circuit for responding to result of selection of the test mode, generating a test pattern in synchronization with a second clock and outputting the test pattern to the circuit to be tested and a comparator circuit for inputting result of test of the circuit to be tested in synchronization with the second clock, and comparing coincidence/non-coincidence between the result of the test and the test pattern supplied to the circuit to be tested. The test circuit further includes an output circuit for holding result of comparison by the comparator circuit and outputting the result of comparison in synchronization with the first clock.

摘要翻译： 测试电路包括输入电路，用于输入数据以选择相对于要测试的电路的测试模式，并输出与第一时钟同步的测试模式的选择结果;模式产生电路，用于响应于所选择的结果 测试模式，与第二时钟同步地产生测试模式，并将测试模式输出到要测试的电路;以及比较器电路，用于与第二时钟同步地输入要测试的电路的测试结果;以及比较符合/ 测试结果与提供给待测电路的测试模式之间不一致。 测试电路还包括输出电路，用于保持比较电路的比较结果，并与第一时钟同步地输出比较结果。

公开(公告)号：US07437645B2

公开(公告)日：2008-10-14

申请号：US11709786

申请日：2007-02-23

申请人： Hiroyuki Fukuyama ,  Takeru Yonaga ,  Hitoshi Tanaka

发明人： Hiroyuki Fukuyama ,  Takeru Yonaga ,  Hitoshi Tanaka

IPC分类号： G01R31/28

CPC分类号： G11C29/30 ,  G11C2029/0405 ,  G11C2029/3202

摘要： A semiconductor test circuit includes an input terminal, a controller, a setting circuit, a command generator, a transmission path switching circuit and a comparator. The input terminal receives a serial data including a command code and a control data. The controller receives a control signal and outputs an internal control signal based on the control signal. The setting circuit receives the serial data and outputs it in response to the internal control signal. The command generator generates an interface signal based on the serial data received from the setting circuit. The switching circuit has ports, receives the signal from one of the ports and outputs the received signal to another one of the ports in response to the internal control signal and the command code. The comparator compares the interface signal received from the command generator with the signal received from the switching circuit.

摘要翻译： 半导体测试电路包括输入端子，控制器，设置电路，命令发生器，传输路径切换电路和比较器。 输入端子接收包括命令码和控制数据的串行数据。 控制器接收控制信号，并根据控制信号输出内部控制信号。 设置电路接收串行数据并根据内部控制信号输出。 命令发生器基于从设置电路接收的串行数据生成接口信号。 开关电路具有端口，从一个端口接收信号，并响应于内部控制信号和命令码将接收的信号输出到另一个端口。 比较器将从命令发生器接收的接口信号与从开关电路接收的信号进行比较。

公开(公告)号：US20070208966A1

公开(公告)日：2007-09-06

申请号：US11709786

申请日：2007-02-23

申请人： Hiroyuki Fukuyama ,  Takeru Yonaga ,  Hitoshi Tanaka

发明人： Hiroyuki Fukuyama ,  Takeru Yonaga ,  Hitoshi Tanaka

IPC分类号： G06K5/04

CPC分类号： G11C29/30 ,  G11C2029/0405 ,  G11C2029/3202

摘要： A semiconductor test circuit includes an input terminal, a controller, a setting circuit, a command generator, a transmission path switching circuit and a comparator. The input terminal receives a serial data including a command code and a control data. The controller receives a control signal and outputs an internal control signal based on the control signal. The setting circuit receives the serial data and outputs it in response to the internal control signal. The command generator generates an interface signal based on the serial data received from the setting circuit. The switching circuit has ports, receives the signal from one of the ports and outputs the received signal to another one of the ports in response to the internal control signal and the command code. The comparator compares the interface signal received from the command generator with the signal received from the switching circuit.

摘要翻译： 半导体测试电路包括输入端子，控制器，设置电路，命令发生器，传输路径切换电路和比较器。 输入端子接收包括命令码和控制数据的串行数据。 控制器接收控制信号，并根据控制信号输出内部控制信号。 设置电路接收串行数据并根据内部控制信号输出。 命令发生器基于从设置电路接收的串行数据生成接口信号。 开关电路具有端口，从一个端口接收信号，并响应于内部控制信号和命令码将接收的信号输出到另一个端口。 比较器将从命令发生器接收的接口信号与从开关电路接收的信号进行比较。

公开(公告)号：US20050240842A1

公开(公告)日：2005-10-27

申请号：US11065370

申请日：2005-02-25

申请人： Takeru Yonaga

发明人： Takeru Yonaga

IPC分类号： G01R31/28 ,  G01R31/317 ,  G11C29/14 ,  G11C29/36 ,  G11C29/40

CPC分类号： G01R31/31723 ,  G01R31/31724 ,  G11C29/14 ,  G11C29/36 ,  G11C29/40 ,  G11C2029/0405 ,  G11C2029/3602

摘要： A test circuit includes: a register circuit, into which data is written after data is cleared in compliance with a reset instruction, the register circuit holding the written data until a subsequent reset instruction is input; a TAP controller which receives a signal for selecting a test mode, and writes the data into the register circuit in accordance with the signal for selecting a test mode in synchronization with a first clock; a pattern generation circuit which generates a test pattern in accordance with the data held in the register circuit, and outputs data based on the test pattern to the circuit to be tested in synchronization with a second clock; and a data comparator which receives data output from the circuit to be tested in synchronization with the second clock, and makes an evaluation of performance in accordance with the test pattern and the data output from the circuit to be tested.

摘要翻译： 测试电路包括：寄存器电路，根据复位指令清除数据后写入数据，寄存器电路保持写入的数据直到输入后续复位指令; TAP控制器，其接收用于选择测试模式的信号，并且根据用于与第一时钟同步地选择测试模式的信号将数据写入寄存器电路; 模式生成电路，其根据保存在所述寄存器电路中的数据生成测试图案，并且根据所述测试图案将数据与第二时钟同步地输出到所述待测电路; 以及数据比较器，其从第二时钟同步地接收从被测电路输出的数据，并根据测试图案和从被测电路输出的数据进行性能评估。

公开(公告)号：US5790470A

公开(公告)日：1998-08-04

申请号：US785601

申请日：1997-01-17

申请人： Takeru Yonaga

发明人： Takeru Yonaga

IPC分类号： G11C11/413 ,  G11C7/10 ,  G11C8/10 ,  G11C11/407 ,  G11C11/408 ,  G11C13/00

CPC分类号： G11C7/1018 ,  G11C8/10

摘要： A decoder circuit prevented from multi-selection is disclosed. The decoder circuit has a pulse generator receiving an external clock signal and outputting a reset signal in response to the external clock signal, address counters receiving the external clock signal and outputting address count signals and address buffers coupled to the address counters respectively. Each of the address buffers receives an external address signal and the address count signal and outputs an internal address signal. The decoder circuit further has address predecoders coupled to the pulse generator and said address buffers. Each of the address predecoders decodes the internal address signals to output a predecode signal in response to the reset signal. The decoder circuit further has an address decoder coupled to the address predecoders. The address decoder decodes the predecode signals to output decode signals.

摘要翻译： 公开了防止多选的解码器电路。 解码器电路具有接收外部时钟信号的脉冲发生器，并响应于外部时钟信号输出复位信号，地址计数器接收外部时钟信号，并分别输出地址计数信号和与地址计数器耦合的地址缓冲器。 每个地址缓冲器接收外部地址信号和地址计数信号并输出​​内部地址信号。 解码器电路还具有耦合到脉冲发生器和所述地址缓冲器的地址预解码器。 每个地址预解码器对内部地址信号进行解码，以响应复位信号输出预解码信号。 解码器电路还具有耦合到地址预解码器的地址解码器。 地址解码器解码预解码信号以输出解码信号。

公开(公告)号：US07225379B2

公开(公告)日：2007-05-29

申请号：US11065370

申请日：2005-02-25

申请人： Takeru Yonaga

发明人： Takeru Yonaga

IPC分类号： G01R31/3193 ,  G06F11/277

CPC分类号： G01R31/31723 ,  G01R31/31724 ,  G11C29/14 ,  G11C29/36 ,  G11C29/40 ,  G11C2029/0405 ,  G11C2029/3602

摘要： A test circuit includes: a register circuit, into which data is written after data is cleared in compliance with a reset instruction, the register circuit holding the written data until a subsequent reset instruction is input; a TAP controller which receives a signal for selecting a test mode, and writes the data into the register circuit in accordance with the signal for selecting a test mode in synchronization with a first clock; a pattern generation circuit which generates a test pattern in accordance with the data held in the register circuit, and outputs data based on the test pattern to the circuit to be tested in synchronization with a second clock; and a data comparator which receives data output from the circuit to be tested in synchronization with the second clock, and makes an evaluation of performance in accordance with the test pattern and the data output from the circuit to be tested.

摘要翻译： 测试电路包括：寄存器电路，根据复位指令清除数据后写入数据，寄存器电路保持写入的数据直到输入后续复位指令; TAP控制器，其接收用于选择测试模式的信号，并且根据用于与第一时钟同步地选择测试模式的信号将数据写入寄存器电路; 模式生成电路，其根据保存在所述寄存器电路中的数据生成测试图案，并且根据所述测试图案将数据与第二时钟同步地输出到所述待测电路; 以及数据比较器，其从第二时钟同步地接收从被测电路输出的数据，并根据测试图案和从被测电路输出的数据进行性能评估。

公开(公告)号：US5444662A

公开(公告)日：1995-08-22

申请号：US257450

申请日：1994-06-08

申请人： Takayuki Tanaka ,  Yoshimasa Sekino ,  Yoshihiro Murashima ,  Yasuhiro Tokunaga ,  Joji Ueno ,  Takeru Yonaga

发明人： Takayuki Tanaka ,  Yoshimasa Sekino ,  Yoshihiro Murashima ,  Yasuhiro Tokunaga ,  Joji Ueno ,  Takeru Yonaga

IPC分类号： G11C11/409 ,  G11C11/4094 ,  G11C7/00

CPC分类号： G11C11/4094

摘要： A dynamic random access memory of the complementary MOS transistor type has memory cells connected between complementary bit lines on one side of a pair of transfer gates and a sense amplifier connected to nodes on the other side of the transfer gates, so that the sense amplifier can be connected to the bit lines and memory cells through the pair of transfer gates. A sense amplifier equalizing circuit and a bit line equalizing circuit are provided on opposite sides of the transfer gates so that the potentials on the bit lines can be equalized independently of equalization of the potentials on the nodes. Accordingly, there is no delay in the equalization due to the transfer gates connecting the nodes to the bit lines. According to another aspect of the invention, the transfer gates each include a pair of MOSFET transistors connected to each other in parallel, wherein one transistor of each pair of MOSFET transistors is an n-channel MOSFET transistor and the other transistor of each pair of MOSFET transistors is a p-channel MOSFET transistor. By, for example, connecting the gate of the NMOS transistor of each transfer to the power source and connecting the gate of each PMOS transistor to the ground, it is possible to prevent erroneous operation of the DRAM from a drop in the gate potential.

摘要翻译： 互补MOS晶体管类型的动态随机存取存储器具有连接在一对传输门的一侧上的互补位线和连接到传输门的另一侧上的节点的读出放大器之间的存储单元，使得读出放大器可以 通过一对传输门连接到位线和存储单元。 感测放大器均衡电路和位线均衡电路设置在传输门的相对侧上，使得可以独立于节点上的电位的均衡来均衡位线上的电位。 因此，由于将节点连接到位线的传输门，所以均衡没有延迟。 根据本发明的另一方面，传输门每个包括彼此并联连接的一对MOSFET晶体管，其中每对MOSFET晶体管中的一个晶体管是n沟道MOSFET晶体管，并且每对MOSFET的另一个晶体管 晶体管是一个p沟道MOSFET晶体管。 例如，通过将每个传输的NMOS晶体管的栅极连接到电源并将每个PMOS晶体管的栅极连接到地，可以防止DRAM的错误操作从栅极电位的下降。