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公开(公告)号：US07760552B2
公开(公告)日：2010-07-20
申请号：US11729216
申请日：2007-03-28
申请人： Hiroyuki Miyake , Mitsuaki Osame , Aya Miyazaki
发明人： Hiroyuki Miyake , Mitsuaki Osame , Aya Miyazaki
IPC分类号： G11C11/34
CPC分类号： G11C16/3436 , G11C16/26
摘要： The present invention provides nonvolatile semiconductor memory devices which operate with low power consumption. In a nonvolatile semiconductor memory device, a plurality of nonvolatile memory elements are connected in series. The plurality of nonvolatile memory elements include a semiconductor layer including a channel forming region and a control gate provided to overlap with the channel forming region. Operations of write, erase, a first read, and a second read in a verify operation of data to the nonvolatile memory elements, are conducted by changing voltage to the control gates of the nonvolatile memory elements. The second read in the verify operation after erase operation is conducted by changing only one of a potential of the control gate of a nonvolatile memory element which are selected from the plurality of nonvolatile memory elements, and as the potential, a potential different from a potential of the first read is used.
摘要翻译： 本发明提供了以低功耗工作的非易失性半导体存储器件。 在非易失性半导体存储器件中，多个非易失性存储器元件串联连接。 多个非易失性存储元件包括包括沟道形成区域的半导体层和设置成与沟道形成区域重叠的控制栅极。 通过将电压改变为非易失性存储器元件的控制栅极来进行对非易失性存储器元件的数据的验证操作的写入，擦除，第一读取和第二次读取操作。 在擦除操作之后的验证操作中的第二次读取是通过仅改变从多个非易失性存储元件中选择的非易失性存储元件的控制栅极的电位中的一个，并且作为电势，与电位不同的电位 的第一次读取被使用。
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公开(公告)号：US20080029807A1
公开(公告)日：2008-02-07
申请号：US11727209
申请日：2007-03-23
IPC分类号： H01L29/788
CPC分类号： H01L29/7881 , H01L21/84 , H01L27/105 , H01L27/11526 , H01L27/11529 , H01L27/12 , H01L29/42324
摘要： A semiconductor device is provided, which comprises at least a cell including a plurality of memory elements connected in series. Each of the plurality of memory elements includes a channel formation region, a source and drain regions, a floating gate, and a control gate. Each of the source and drain regions is electrically connected to an erasing line through a semiconductor impurity region.
摘要翻译： 提供一种半导体器件，其包括至少一个包括串联连接的多个存储元件的单元。 多个存储元件中的每一个包括沟道形成区域，源极和漏极区域，浮动栅极和控制栅极。 源区和漏区中的每一个通过半导体杂质区电连接到擦除线。
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公开(公告)号：US08325526B2
公开(公告)日：2012-12-04
申请号：US12700802
申请日：2010-02-05
IPC分类号： G11C16/04
CPC分类号： H01L29/7881 , H01L21/84 , H01L27/105 , H01L27/11526 , H01L27/11529 , H01L27/12 , H01L29/42324
摘要： A semiconductor device is provided, which comprises at least a cell including a plurality of memory elements connected in series. Each of the plurality of memory elements includes a channel formation region, a source and drain regions, a floating gate, and a control gate. Each of the source and drain regions is electrically connected to an erasing line through a semiconductor impurity region.
摘要翻译： 提供一种半导体器件，其包括至少一个包括串联连接的多个存储元件的单元。 多个存储元件中的每一个包括沟道形成区域，源极和漏极区域，浮动栅极和控制栅极。 源区和漏区中的每一个通过半导体杂质区电连接到擦除线。
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公开(公告)号：US20100277985A1
公开(公告)日：2010-11-04
申请号：US12836243
申请日：2010-07-14
申请人： Hiroyuki Miyake , Mitsuaki Osame , Aya Miyazaki
发明人： Hiroyuki Miyake , Mitsuaki Osame , Aya Miyazaki
IPC分类号： G11C16/06
CPC分类号： G11C16/3436 , G11C16/26
摘要： The present invention provides nonvolatile semiconductor memory devices which operate with low power consumption. In a nonvolatile semiconductor memory device, a plurality of nonvolatile memory elements are connected in series. The plurality of nonvolatile memory elements include a semiconductor layer including a channel forming region and a control gate provided to overlap with the channel forming region. Operations of write, erase, a first read, and a second read in a verify operation of data to the nonvolatile memory elements, are conducted by changing voltage to the control gates of the nonvolatile memory elements. The second read in the verify operation after erase operation is conducted by changing only one of a potential of the control gate of a nonvolatile memory element which are selected from the plurality of nonvolatile memory elements, and as the potential, a potential different from a potential of the first read is used.
摘要翻译： 本发明提供了以低功耗工作的非易失性半导体存储器件。 在非易失性半导体存储器件中，多个非易失性存储元件串联连接。 多个非易失性存储元件包括包括沟道形成区域的半导体层和设置成与沟道形成区域重叠的控制栅极。 通过将电压改变为非易失性存储器元件的控制栅极来进行对非易失性存储器元件的数据的验证操作的写入，擦除，第一读取和第二次读取操作。 在擦除操作之后的验证操作中的第二次读取是通过仅改变从多个非易失性存储元件中选择的非易失性存储元件的控制栅极的电位中的一个，并且作为电势，与电位不同的电位 的第一次读取被使用。
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公开(公告)号：US07554854B2
公开(公告)日：2009-06-30
申请号：US11716672
申请日：2007-03-12
IPC分类号： G11C16/04
CPC分类号： G11C16/14 , G11C8/10 , G11C16/0483 , G11C16/08 , H01L21/28273 , H01L27/105 , H01L27/11519 , H01L27/11526 , H01L27/11529 , H01L27/11546
摘要： To provide a method of releasing charges which have been injected into charge accumulating layers of nonvolatile memory elements without using a substrate terminal such as a p well or an n well, as a method for deleting data from a NAND-type nonvolatile memory. In the method for deleting data from the NAND-type nonvolatile memory, charges stored in a charge accumulating layer of a first nonvolatile memory element are released by applying a first potential to a bit line and a source line, a second potential to a control gate of the first nonvolatile memory element, and a third potential which is different from the second potential to a control gate of a second nonvolatile memory element.
摘要翻译： 作为从NAND型非易失性存储器中删除数据的方法，提供一种释放已经注入到非易失性存储元件的电荷累积层中而不使用诸如p阱或n阱的衬底端子的电荷的方法。 在从NAND型非易失性存储器中删除数据的方法中，通过将第一电位施加到位线和源极线，将第二电位施加到控制栅极来释放存储在第一非易失性存储元件的电荷累积层中的电荷 以及与第二电位不同的第三电位连接到第二非易失性存储元件的控制栅极。
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公开(公告)号：US08018776B2
公开(公告)日：2011-09-13
申请号：US12836243
申请日：2010-07-14
申请人： Hiroyuki Miyake , Mitsuaki Osame , Aya Miyazaki
发明人： Hiroyuki Miyake , Mitsuaki Osame , Aya Miyazaki
IPC分类号： G11C11/34
CPC分类号： G11C16/3436 , G11C16/26
摘要： The present invention provides nonvolatile semiconductor memory devices which operate with low power consumption. In a nonvolatile semiconductor memory device, a plurality of nonvolatile memory elements are connected in series. The plurality of nonvolatile memory elements include a semiconductor layer including a channel forming region and a control gate provided to overlap with the channel forming region. Operations of write, erase, a first read, and a second read in a verify operation of data to the nonvolatile memory elements, are conducted by changing voltage to the control gates of the nonvolatile memory elements. The second read in the verify operation after erase operation is conducted by changing only one of a potential of the control gate of a nonvolatile memory element which are selected from the plurality of nonvolatile memory elements, and as the potential, a potential different from a potential of the first read is used.
摘要翻译： 本发明提供了以低功耗工作的非易失性半导体存储器件。 在非易失性半导体存储器件中，多个非易失性存储元件串联连接。 多个非易失性存储元件包括包括沟道形成区域的半导体层和设置成与沟道形成区域重叠的控制栅极。 通过将电压改变为非易失性存储器元件的控制栅极来进行对非易失性存储器元件的数据的验证操作的写入，擦除，第一读取和第二次读取操作。 在擦除操作之后的验证操作中的第二次读取是通过仅改变从多个非易失性存储元件中选择的非易失性存储元件的控制栅极的电位中的一个，并且作为电势，与电位不同的电位 的第一次读取被使用。
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公开(公告)号：US07961525B2
公开(公告)日：2011-06-14
申请号：US12491395
申请日：2009-06-25
IPC分类号： G11C16/04
CPC分类号： G11C16/14 , G11C8/10 , G11C16/0483 , G11C16/08 , H01L21/28273 , H01L27/105 , H01L27/11519 , H01L27/11526 , H01L27/11529 , H01L27/11546
摘要： To provide a method of releasing charges which have been injected into charge accumulating layers of nonvolatile memory elements without using a substrate terminal such as a p well or an n well, as a method for deleting data from a NAND-type nonvolatile memory. In the method for deleting data from the NAND-type nonvolatile memory, charges stored in a charge accumulating layer of a first nonvolatile memory element are released by applying a first potential to a bit line and a source line, a second potential to a control gate of the first nonvolatile memory element, and a third potential which is different from the second potential to a control gate of a second nonvolatile memory element.
摘要翻译： 作为从NAND型非易失性存储器中删除数据的方法，提供一种释放已经注入到非易失性存储元件的电荷累积层中而不使用诸如p阱或n阱的衬底端子的电荷的方法。 在从NAND型非易失性存储器中删除数据的方法中，通过将第一电位施加到位线和源极线，将第二电位施加到控制栅极来释放存储在第一非易失性存储元件的电荷累积层中的电荷 以及与第二电位不同的第三电位连接到第二非易失性存储元件的控制栅极。
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公开(公告)号：US07692973B2
公开(公告)日：2010-04-06
申请号：US11727209
申请日：2007-03-23
IPC分类号： G11C11/03
CPC分类号： H01L29/7881 , H01L21/84 , H01L27/105 , H01L27/11526 , H01L27/11529 , H01L27/12 , H01L29/42324
摘要： A semiconductor device is provided, which comprises at least a cell including a plurality of memory elements connected in series. Each of the plurality of memory elements includes a channel formation region, source and drain regions, a floating gate, and a control gate. Each of the source and drain regions is electrically connected to an erasing line through a semiconductor impurity region.
摘要翻译： 提供一种半导体器件，其包括至少一个包括串联连接的多个存储元件的单元。 多个存储元件中的每一个包括沟道形成区域，源极和漏极区域，浮动栅极和控制栅极。 源区和漏区中的每一个通过半导体杂质区电连接到擦除线。
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公开(公告)号：US20090257283A1
公开(公告)日：2009-10-15
申请号：US12491395
申请日：2009-06-25
IPC分类号： G11C16/04 , H01L29/792
CPC分类号： G11C16/14 , G11C8/10 , G11C16/0483 , G11C16/08 , H01L21/28273 , H01L27/105 , H01L27/11519 , H01L27/11526 , H01L27/11529 , H01L27/11546
摘要： To provide a method of releasing charges which have been injected into charge accumulating layers of nonvolatile memory elements without using a substrate terminal such as a p well or an n well, as a method for deleting data from a NAND-type nonvolatile memory. In the method for deleting data from the NAND-type nonvolatile memory, charges stored in a charge accumulating layer of a first nonvolatile memory element are released by applying a first potential to a bit line and a source line, a second potential to a control gate of the first nonvolatile memory element, and a third potential which is different from the second potential to a control gate of a second nonvolatile memory element.
摘要翻译： 作为从NAND型非易失性存储器中删除数据的方法，提供一种释放已经注入到非易失性存储元件的电荷累积层中而不使用诸如p阱或n阱的衬底端子的电荷的方法。 在从NAND型非易失性存储器中删除数据的方法中，通过将第一电位施加到位线和源极线，将第二电位施加到控制栅极来释放存储在第一非易失性存储元件的电荷累积层中的电荷 以及与第二电位不同的第三电位连接到第二非易失性存储元件的控制栅极。
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公开(公告)号：US20070230254A1
公开(公告)日：2007-10-04
申请号：US11716672
申请日：2007-03-12
CPC分类号： G11C16/14 , G11C8/10 , G11C16/0483 , G11C16/08 , H01L21/28273 , H01L27/105 , H01L27/11519 , H01L27/11526 , H01L27/11529 , H01L27/11546
摘要： To provide a method of releasing charges which have been injected into charge accumulating layers of nonvolatile memory elements without using a substrate terminal such as a p well or an n well, as a method for deleting data from a NAND-type nonvolatile memory. In the method for deleting data from the NAND-type nonvolatile memory, charges stored in a charge accumulating layer of a first nonvolatile memory element are released by applying a first potential to a bit line and a source line, a second potential to a control gate of the first nonvolatile memory element, and a third potential which is different from the second potential to a control gate of a second nonvolatile memory element.
摘要翻译： 作为从NAND型非易失性存储器中删除数据的方法，提供一种释放已经注入到非易失性存储元件的电荷累积层中而不使用诸如p阱或n阱的衬底端子的电荷的方法。 在从NAND型非易失性存储器中删除数据的方法中，通过将第一电位施加到位线和源极线，将第二电位施加到控制栅极来释放存储在第一非易失性存储元件的电荷累积层中的电荷 以及与第二电位不同的第三电位连接到第二非易失性存储元件的控制栅极。
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