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公开(公告)号：US20080029807A1
公开(公告)日：2008-02-07
申请号：US11727209
申请日：2007-03-23
IPC分类号： H01L29/788
CPC分类号： H01L29/7881 , H01L21/84 , H01L27/105 , H01L27/11526 , H01L27/11529 , H01L27/12 , H01L29/42324
摘要： A semiconductor device is provided, which comprises at least a cell including a plurality of memory elements connected in series. Each of the plurality of memory elements includes a channel formation region, a source and drain regions, a floating gate, and a control gate. Each of the source and drain regions is electrically connected to an erasing line through a semiconductor impurity region.
摘要翻译： 提供一种半导体器件，其包括至少一个包括串联连接的多个存储元件的单元。 多个存储元件中的每一个包括沟道形成区域，源极和漏极区域，浮动栅极和控制栅极。 源区和漏区中的每一个通过半导体杂质区电连接到擦除线。
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公开(公告)号：US08212304B2
公开(公告)日：2012-07-03
申请号：US13114556
申请日：2011-05-24
IPC分类号： H01L29/76
CPC分类号： G11C16/14 , G11C8/10 , G11C16/0483 , G11C16/08 , H01L21/28273 , H01L27/105 , H01L27/11519 , H01L27/11526 , H01L27/11529 , H01L27/11546
摘要： To provide a method of releasing charges which have been injected into charge accumulating layers of nonvolatile memory elements without using a substrate terminal such as a p well or an n well, as a method for deleting data from a NAND-type nonvolatile memory. In the method for deleting data from the NAND-type nonvolatile memory, charges stored in a charge accumulating layer of a first nonvolatile memory element are released by applying a first potential to a bit line and a source line, a second potential to a control gate of the first nonvolatile memory element, and a third potential which is different from the second potential to a control gate of a second nonvolatile memory element.
摘要翻译： 作为从NAND型非易失性存储器中删除数据的方法，提供一种释放已经注入到非易失性存储元件的电荷累积层中而不使用诸如p阱或n阱的衬底端子的电荷的方法。 在从NAND型非易失性存储器中删除数据的方法中，通过将第一电位施加到位线和源极线，将第二电位施加到控制栅极来释放存储在第一非易失性存储元件的电荷累积层中的电荷 以及与第二电位不同的第三电位连接到第二非易失性存储元件的控制栅极。
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公开(公告)号：US08325526B2
公开(公告)日：2012-12-04
申请号：US12700802
申请日：2010-02-05
IPC分类号： G11C16/04
CPC分类号： H01L29/7881 , H01L21/84 , H01L27/105 , H01L27/11526 , H01L27/11529 , H01L27/12 , H01L29/42324
摘要： A semiconductor device is provided, which comprises at least a cell including a plurality of memory elements connected in series. Each of the plurality of memory elements includes a channel formation region, a source and drain regions, a floating gate, and a control gate. Each of the source and drain regions is electrically connected to an erasing line through a semiconductor impurity region.
摘要翻译： 提供一种半导体器件，其包括至少一个包括串联连接的多个存储元件的单元。 多个存储元件中的每一个包括沟道形成区域，源极和漏极区域，浮动栅极和控制栅极。 源区和漏区中的每一个通过半导体杂质区电连接到擦除线。
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公开(公告)号：US07554854B2
公开(公告)日：2009-06-30
申请号：US11716672
申请日：2007-03-12
IPC分类号： G11C16/04
CPC分类号： G11C16/14 , G11C8/10 , G11C16/0483 , G11C16/08 , H01L21/28273 , H01L27/105 , H01L27/11519 , H01L27/11526 , H01L27/11529 , H01L27/11546
摘要： To provide a method of releasing charges which have been injected into charge accumulating layers of nonvolatile memory elements without using a substrate terminal such as a p well or an n well, as a method for deleting data from a NAND-type nonvolatile memory. In the method for deleting data from the NAND-type nonvolatile memory, charges stored in a charge accumulating layer of a first nonvolatile memory element are released by applying a first potential to a bit line and a source line, a second potential to a control gate of the first nonvolatile memory element, and a third potential which is different from the second potential to a control gate of a second nonvolatile memory element.
摘要翻译： 作为从NAND型非易失性存储器中删除数据的方法，提供一种释放已经注入到非易失性存储元件的电荷累积层中而不使用诸如p阱或n阱的衬底端子的电荷的方法。 在从NAND型非易失性存储器中删除数据的方法中，通过将第一电位施加到位线和源极线，将第二电位施加到控制栅极来释放存储在第一非易失性存储元件的电荷累积层中的电荷 以及与第二电位不同的第三电位连接到第二非易失性存储元件的控制栅极。
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公开(公告)号：US07961525B2
公开(公告)日：2011-06-14
申请号：US12491395
申请日：2009-06-25
IPC分类号： G11C16/04
CPC分类号： G11C16/14 , G11C8/10 , G11C16/0483 , G11C16/08 , H01L21/28273 , H01L27/105 , H01L27/11519 , H01L27/11526 , H01L27/11529 , H01L27/11546
摘要： To provide a method of releasing charges which have been injected into charge accumulating layers of nonvolatile memory elements without using a substrate terminal such as a p well or an n well, as a method for deleting data from a NAND-type nonvolatile memory. In the method for deleting data from the NAND-type nonvolatile memory, charges stored in a charge accumulating layer of a first nonvolatile memory element are released by applying a first potential to a bit line and a source line, a second potential to a control gate of the first nonvolatile memory element, and a third potential which is different from the second potential to a control gate of a second nonvolatile memory element.
摘要翻译： 作为从NAND型非易失性存储器中删除数据的方法，提供一种释放已经注入到非易失性存储元件的电荷累积层中而不使用诸如p阱或n阱的衬底端子的电荷的方法。 在从NAND型非易失性存储器中删除数据的方法中，通过将第一电位施加到位线和源极线，将第二电位施加到控制栅极来释放存储在第一非易失性存储元件的电荷累积层中的电荷 以及与第二电位不同的第三电位连接到第二非易失性存储元件的控制栅极。
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公开(公告)号：US07692973B2
公开(公告)日：2010-04-06
申请号：US11727209
申请日：2007-03-23
IPC分类号： G11C11/03
CPC分类号： H01L29/7881 , H01L21/84 , H01L27/105 , H01L27/11526 , H01L27/11529 , H01L27/12 , H01L29/42324
摘要： A semiconductor device is provided, which comprises at least a cell including a plurality of memory elements connected in series. Each of the plurality of memory elements includes a channel formation region, source and drain regions, a floating gate, and a control gate. Each of the source and drain regions is electrically connected to an erasing line through a semiconductor impurity region.
摘要翻译： 提供一种半导体器件，其包括至少一个包括串联连接的多个存储元件的单元。 多个存储元件中的每一个包括沟道形成区域，源极和漏极区域，浮动栅极和控制栅极。 源区和漏区中的每一个通过半导体杂质区电连接到擦除线。
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公开(公告)号：US20090257283A1
公开(公告)日：2009-10-15
申请号：US12491395
申请日：2009-06-25
IPC分类号： G11C16/04 , H01L29/792
CPC分类号： G11C16/14 , G11C8/10 , G11C16/0483 , G11C16/08 , H01L21/28273 , H01L27/105 , H01L27/11519 , H01L27/11526 , H01L27/11529 , H01L27/11546
摘要： To provide a method of releasing charges which have been injected into charge accumulating layers of nonvolatile memory elements without using a substrate terminal such as a p well or an n well, as a method for deleting data from a NAND-type nonvolatile memory. In the method for deleting data from the NAND-type nonvolatile memory, charges stored in a charge accumulating layer of a first nonvolatile memory element are released by applying a first potential to a bit line and a source line, a second potential to a control gate of the first nonvolatile memory element, and a third potential which is different from the second potential to a control gate of a second nonvolatile memory element.
摘要翻译： 作为从NAND型非易失性存储器中删除数据的方法，提供一种释放已经注入到非易失性存储元件的电荷累积层中而不使用诸如p阱或n阱的衬底端子的电荷的方法。 在从NAND型非易失性存储器中删除数据的方法中，通过将第一电位施加到位线和源极线，将第二电位施加到控制栅极来释放存储在第一非易失性存储元件的电荷累积层中的电荷 以及与第二电位不同的第三电位连接到第二非易失性存储元件的控制栅极。
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公开(公告)号：US20070230254A1
公开(公告)日：2007-10-04
申请号：US11716672
申请日：2007-03-12
CPC分类号： G11C16/14 , G11C8/10 , G11C16/0483 , G11C16/08 , H01L21/28273 , H01L27/105 , H01L27/11519 , H01L27/11526 , H01L27/11529 , H01L27/11546
摘要： To provide a method of releasing charges which have been injected into charge accumulating layers of nonvolatile memory elements without using a substrate terminal such as a p well or an n well, as a method for deleting data from a NAND-type nonvolatile memory. In the method for deleting data from the NAND-type nonvolatile memory, charges stored in a charge accumulating layer of a first nonvolatile memory element are released by applying a first potential to a bit line and a source line, a second potential to a control gate of the first nonvolatile memory element, and a third potential which is different from the second potential to a control gate of a second nonvolatile memory element.
摘要翻译： 作为从NAND型非易失性存储器中删除数据的方法，提供一种释放已经注入到非易失性存储元件的电荷累积层中而不使用诸如p阱或n阱的衬底端子的电荷的方法。 在从NAND型非易失性存储器中删除数据的方法中，通过将第一电位施加到位线和源极线，将第二电位施加到控制栅极来释放存储在第一非易失性存储元件的电荷累积层中的电荷 以及与第二电位不同的第三电位连接到第二非易失性存储元件的控制栅极。
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公开(公告)号：US20070152925A1
公开(公告)日：2007-07-05
申请号：US11701346
申请日：2007-02-01
申请人： Mitsuaki Osame , Aya Miyazaki , Yoshifumi Tanada , Keisuke Miyagawa , Satoshi Seo , Shunpei Yamazaki
发明人： Mitsuaki Osame , Aya Miyazaki , Yoshifumi Tanada , Keisuke Miyagawa , Satoshi Seo , Shunpei Yamazaki
IPC分类号： G09G3/30
CPC分类号： G09G3/32 , G09G3/3233 , G09G3/3258 , G09G3/3266 , G09G3/3291 , G09G2300/043 , G09G2300/0819 , G09G2300/0842 , G09G2300/0861 , G09G2310/0251 , G09G2310/0256 , G09G2310/027 , G09G2310/061 , G09G2310/08 , G09G2320/043 , G09G2320/045 , H01L33/0041
摘要： A light emitting device that achieves long life, and which is capable of performing high duty drive, by suppressing initial light emitting element deterioration is provided. Reverse bias application to an EL element (109) is performed one row at a time by forming a reverse bias electric power source line (112) and a reverse bias TFT (108). Reverse bias application can therefore be performed in synchronous with operations for write-in of an image signal, light emission, erasure, and the like. Reverse bias application therefore becomes possible while maintaining a duty equivalent to that of a conventional driving method.
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公开(公告)号：US07450093B2
公开(公告)日：2008-11-11
申请号：US11701346
申请日：2007-02-01
申请人： Mitsuaki Osame , Aya Miyazaki , Yoshifumi Tanada , Keisuke Miyagawa , Satoshi Seo , Shunpei Yamazaki
发明人： Mitsuaki Osame , Aya Miyazaki , Yoshifumi Tanada , Keisuke Miyagawa , Satoshi Seo , Shunpei Yamazaki
CPC分类号： G09G3/32 , G09G3/3233 , G09G3/3258 , G09G3/3266 , G09G3/3291 , G09G2300/043 , G09G2300/0819 , G09G2300/0842 , G09G2300/0861 , G09G2310/0251 , G09G2310/0256 , G09G2310/027 , G09G2310/061 , G09G2310/08 , G09G2320/043 , G09G2320/045 , H01L33/0041
摘要： A light emitting device that achieves long life, and which is capable of performing high duty drive, by suppressing initial light emitting element deterioration is provided. Reverse bias application to an EL element (109) is performed one row at a time by forming a reverse bias electric power source line (112) and a reverse bias TFT (108). Reverse bias application can therefore be performed in synchronous with operations for write-in of an image signal, light emission, erasure, and the like. Reverse bias application therefore becomes possible while maintaining a duty equivalent to that of a conventional driving method.
摘要翻译： 提供了通过抑制初始发光元件劣化而实现长寿命并能够进行高占空比驱动的发光器件。 通过形成反向偏置电源线（112）和反向偏压TFT（108），一次对一个EL元件（109）施加反向偏置。 因此，可以与图像信号的写入，发光，擦除等的操作同步地执行反向偏置应用。 因此，在保持与常规驱动方法相同的占空比的情况下，可以实现反向偏置应用。
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