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    Dynamic random access memory device suppressing need for voltage-boosting current consumption
    3.
    发明授权
    Dynamic random access memory device suppressing need for voltage-boosting current consumption 有权
    动态随机存取存储器件抑制升压电流消耗的需要

    公开(公告)号：US07864598B2

    公开(公告)日：2011-01-04

    申请号：US12025066

    申请日：2008-02-04

    申请人： Hiroyuki Takahashi ,  Atsushi Nakagawa

    发明人： Hiroyuki Takahashi ,  Atsushi Nakagawa

    IPC分类号： G11C5/14

    CPC分类号： G11C11/4099 ,  G11C7/065 ,  G11C7/12 ,  G11C7/14 ,  G11C11/4091 ,  G11C11/4094

    摘要： In one embodiment, a semiconductor memory device includes a plurality of pairs of bit lines, each of said pairs including a first bit line, a second bit line, a memory cell coupled to said first bit line, a sense amplifier determining the logical value stored in the memory cell according to a potential difference between the first and the second bit line, a reference voltage generation circuit, and a reference voltage supply switch coupling an output of the reference voltage generation circuit to the second bit line.

    摘要翻译： 在一个实施例中，半导体存储器件包括多对位线，所述对中的每一对包括第一位线，第二位线，耦合到所述第一位线的存储器单元，确定存储的逻辑值的读出放大器 根据第一和第二位线之间的电位差，参考电压产生电路和将参考电压产生电路的输出耦合到第二位线的参考电压供应开关在存储单元中。

    Semiconductor storage device
    4.
    发明申请
    Semiconductor storage device 失效
    半导体存储设备

    公开(公告)号：US20090073744A1

    公开(公告)日：2009-03-19

    申请号：US12232159

    申请日：2008-09-11

    申请人： Hiroyuki Takahashi ,  Atsushi Nakagawa

    发明人： Hiroyuki Takahashi ,  Atsushi Nakagawa

    IPC分类号： G11C11/24 ,  G11C5/14 ,  G11C8/00

    CPC分类号： G11C5/145 ,  G11C7/02 ,  G11C8/08 ,  G11C11/4074 ,  G11C11/4085

    摘要： A semiconductor storage device according to one aspect of the present invention includes a DRAM cell including one transistor and one capacitor, in which one of a first voltage and a second voltage is applied to a gate of the transistor, the first voltage being a selected voltage, and the second voltage being a non-selected voltage, a voltage difference between the first voltage and the second voltage is larger than a voltage difference between a power supply voltage and a ground voltage, and one of the ground voltage and the power supply voltage which is closer to the non-selected voltage is applied to a back gate of the transistor irrespective of selection or non-selection.

    摘要翻译： 根据本发明的一个方面的半导体存储装置包括：DRAM单元，包括一个晶体管和一个电容器，其中第一电压和第二电压中的一个施加到晶体管的栅极，第一电压是选定的电压 ，第二电压为非选择电压时，第一电压与第二电压之间的电压差大于电源电压与接地电压之间的电压差，接地电压和电源电压之一 更接近于非选择电压的电压施加到晶体管的背栅极，而与选择或非选择无关。

    Semiconductor device that uses a plurality of source voltages
    5.
    发明申请
    Semiconductor device that uses a plurality of source voltages 有权
    使用多个源电压的半导体器件

    公开(公告)号：US20080291750A1

    公开(公告)日：2008-11-27

    申请号：US12153814

    申请日：2008-05-23

    申请人： Hiroyuki Takahashi ,  Atsushi Nakagawa

    发明人： Hiroyuki Takahashi ,  Atsushi Nakagawa

    IPC分类号： G11C5/14

    CPC分类号： G11C5/145 ,  G11C29/02 ,  G11C29/021 ,  G11C29/028

    摘要： A semiconductor device includes a first memory; and a voltage adjusting portion configured to receive a first voltage, a second voltage higher than the first voltage, and a third voltage higher than the second voltage. The first memory includes: a memory cell configured to be connected to a word line and a bit line, a word-line driving circuit configured to drive the word line, and a sense amplifier configured to sense information stored in the memory cell. The voltage adjusting portion includes: a voltage modifying circuit configured to step down or boost up the third voltage at a predetermined mode to generate a fourth voltage higher than the second voltage, and supply the fourth voltage to the sense amplifier or the word-line driving circuit.

    摘要翻译： 半导体器件包括第一存储器; 以及电压调整部，被配置为接收第一电压，高于第一电压的第二电压以及高于第二电压的第三电压。 第一存储器包括：配置为连接到字线和位线的存储单元，被配置为驱动字线的字线驱动电路，以及被配置为感测存储在存储单元中的信息的读出放大器。 电压调整部包括：电压修正电路，被配置为以预定模式降压或提升第三电压，以产生高于第二电压的第四电压，并将第四电压提供给读出放大器或字线驱动 电路。

    Non-synchronous semiconductor memory device having page mode read/write
    6.
    发明授权
    Non-synchronous semiconductor memory device having page mode read/write 有权
    具有页模式读/写的非同步半导体存储器件

    公开(公告)号：US07054224B2

    公开(公告)日：2006-05-30

    申请号：US10478369

    申请日：2002-05-23

    申请人： Hiroyuki Takahashi ,  Hideo Inaba ,  Atsushi Nakagawa

    发明人： Hiroyuki Takahashi ,  Hideo Inaba ,  Atsushi Nakagawa

    IPC分类号： G11C8/00

    CPC分类号： G11C11/40615 ,  G11C7/1012 ,  G11C7/1051 ,  G11C11/406 ,  G11C11/4096

    摘要： The present invention provides a non-synchronous semiconductor memory device configured as a pseudo-SRAM and capable of relaxing the limitation to address skew and improving the read rate. A data latch circuit 110 holds data having been read out of memory cells in a memory cell array 106 designated by a tow address included in an address ADD in a read mode. Upon transitions of column addresses A0, A1 included in the address, a multiplexer 111 sequentially and non-synchronously feeds out the data held in the data latch circuit 110 based on the column addresses A0, A1.

    摘要翻译： 本发明提供一种被配置为伪SRAM的非同步半导体存储器件，并且能够放宽对寻址偏移的限制并提高读取速率。 数据锁存电路110将从存储单元读出的数据保存在由读取模式中包含在地址ADD中的拖尾地址指定的存储单元阵列106中。 在地址中包括的列地址A 0，A 1的转换中，多路复用器111基于列地址A 0，A 1顺序地并且不同步地馈送保存在数据锁存电路110中的数据。

    Semiconductor memory device
    7.
    发明申请
    Semiconductor memory device 有权
    半导体存储器件

    公开(公告)号：US20050207214A1

    公开(公告)日：2005-09-22

    申请号：US11130464

    申请日：2005-05-16

    申请人： Hiroyuki Takahashi ,  Atsushi Nakagawa ,  Hideo Inaba

    发明人： Hiroyuki Takahashi ,  Atsushi Nakagawa ,  Hideo Inaba

    IPC分类号： G06F1/32 ,  G11C11/403 ,  G11C11/406 ,  G11C11/407 ,  G11C11/4074 ,  G11C11/00

    CPC分类号： G11C11/40615 ,  G11C11/406 ,  G11C11/4074 ,  G11C2207/2227 ,  G11C2211/4067

    摘要： A semiconductor memory device is provided which effectively reduces a consumption of current of a system of circuits associated with refresh operations. A control signal circuit 2 controls n-channel transistors 3C, 4B to be in an OFF-state based on an internal chip select signal SCI in an interval time period between the refresh operations, wherein the n-channel transistors 3C, 4B are connected between the system of circuits associated with refresh operations (an internal voltage-down circuit 3 and a boost circuit 4) and the ground, so as to break down a leak path of the system of circuits associated with refresh operations for reducing the leakage of current. At a timing of starting the refresh operation by triggering a timer, the internal chip select signal SCI is transitioned to a high level for supplying a ground voltage to the internal voltage-down circuit 3 and the boost circuit 4.

    摘要翻译： 提供一种半导体存储器件，其有效地减少与刷新操作相关的电路系统的电流消耗。 在刷新操作之间的间隔时间内，控制信号电路2基于内部片选信号SCI控制n沟道晶体管3C，4B处于截止状态，其中n沟道晶体管3 C，4 B连接在与刷新操作（内部降压电路3和升压电路4）相关联的电路系统和地之间，以便分解与刷新操作相关联的电路系统的泄漏路径，以减少 电流泄漏。 在通过触发定时器开始刷新操作的定时，内部芯片选择信号SCI转换到用于向内部降压电路3和升压电路4提供接地电压的高电平。

    Semiconductor memory device
    8.
    发明授权
    Semiconductor memory device 有权
    半导体存储器件

    公开(公告)号：US06947345B2

    公开(公告)日：2005-09-20

    申请号：US10473656

    申请日：2002-03-28

    申请人： Hiroyuki Takahashi ,  Hideo Inaba ,  Atsushi Nakagawa

    发明人： Hiroyuki Takahashi ,  Hideo Inaba ,  Atsushi Nakagawa

    IPC分类号： G11C7/22 ,  G11C11/406 ,  G11C11/4076 ,  G11C7/00

    CPC分类号： G11C11/40615 ,  G11C7/22 ,  G11C11/406 ,  G11C11/4076 ,  G11C2207/2227 ,  G11C2211/4061 ,  G11C2211/4067

    摘要： A semiconductor memory device is provided, which is capable of effectively reducing a current comsumption caused by a self-refresh operation in a stand-by mode.In the refresh operation in the stand-by mode, under the control by a refresh control circuit 8B, firstly, a suppression is made for current driving abilities of sense amplifiers 70A˜70D provided for amplifying data signals appearing on bit lines, and secondly, an expansion is made of a pulse width of a row enable signal RE, which defines a period of time for selecting word lines WL, and thirdly, parallel activations of plural word lines are made based on the row enable signal RE with the expanded pulse width, thereby reducing the frequency of operations of the circuit system associated with the refresh operations, resulting in a suppression of the current consumption.

    摘要翻译： 提供一种半导体存储器件，其能够有效地降低由待机模式中的自刷新操作引起的电流消耗。 在待机模式的刷新操作中，在刷新控制电路8B的控制下，首先抑制用于放大位线上出现的数据信号的读出放大器70A〜70D的电流驱动能力， 其次，扩展行限制信号RE的脉冲宽度，该行允许信号RE定义了用于选择字线WL的时间段，第三，基于行允许信号RE进行多条字线的并行激活， 扩大的脉冲宽度，从而降低与刷新操作相关联的电路系统的操作频率，导致电流消耗的抑制。

    Timer circuit and semiconductor memory incorporating the timer circuit
    9.
    发明授权
    Timer circuit and semiconductor memory incorporating the timer circuit 有权
    定时器电路和半导体存储器结合定时器电路

    公开(公告)号：US06856566B2

    公开(公告)日：2005-02-15

    申请号：US10343806

    申请日：2001-08-03

    申请人： Hiroyuki Takahashi ,  Masatoshi Sonoda ,  Atsushi Nakagawa

    发明人： Hiroyuki Takahashi ,  Masatoshi Sonoda ,  Atsushi Nakagawa

    IPC分类号： G11C5/00 ,  G11C7/22 ,  G11C8/18 ,  G11C11/406 ,  G11C11/4074 ,  G11C11/4076 ,  H03K3/011 ,  H03K3/03 ,  G11C7/00

    CPC分类号： H03K3/0315 ,  G11C7/04 ,  G11C7/22 ,  G11C7/222 ,  G11C8/18 ,  G11C11/406 ,  G11C11/40626 ,  G11C11/4074 ,  G11C11/4076 ,  H03K3/011

    摘要： It is an object to provide a timer circuit which exhibits a tendency of decreasing a timer cycle upon a temperature increase and another tendency of increasing the timer cycle upon a temperature decrease. A diode D has a current characteristic depending upon temperature. A forward current flows through an n-type MOS transistor N1 which forms a primary side of a current mirror. Another current flowing through a p-type MOS transistor P2 and an n-type MOS transistor N3 which form a secondary side of the current mirror is defined depending upon the current flowing through the n-type MOS transistor N1. The current flowing through the p-type MOS transistor P2 and the n-type MOS transistor N3 is supplied as an operating current of a ring oscillator comprising inverters I1˜I3. Accordingly, a cycle (timer cycle) of a clock signal CLK outputted from this ring oscillator reflects a temperature characteristic of the diode D, wherein the timer cycle is decreased with increasing the temperature.

    摘要翻译： 本发明的目的是提供一种定时器电路，其在温度升高时呈现减小定时器周期的趋势，以及在温度降低时增加定时器周期的另一趋势。 二极管D具有取决于温度的电流特性。 正向电流流过形成电流镜的初级侧的n型MOS晶体管N1。 形成电流镜的二次侧的p型MOS晶体管P2和n型MOS晶体管N3的另一个电流根据流经n型MOS晶体管N1的电流而定义。 流过p型MOS晶体管P2和n型MOS晶体管N3的电流作为包括反相器I1〜I3的环形振荡器的工作电流提供。 因此，从该环形振荡器输出的时钟信号CLK的周期（定时器周期）反映二极管D的温度特性，其中定时器周期随着温度的升高而降低。

    Semiconductor storage device
    10.
    发明授权
    Semiconductor storage device 失效
    半导体存储设备

    公开(公告)号：US07852704B2

    公开(公告)日：2010-12-14

    申请号：US12232159

    申请日：2008-09-11

    申请人： Hiroyuki Takahashi ,  Atsushi Nakagawa

    发明人： Hiroyuki Takahashi ,  Atsushi Nakagawa

    IPC分类号： G11C8/00

    CPC分类号： G11C5/145 ,  G11C7/02 ,  G11C8/08 ,  G11C11/4074 ,  G11C11/4085

    摘要： A semiconductor storage device according to one aspect of the present invention includes a DRAM cell including one transistor and one capacitor, in which one of a first voltage and a second voltage is applied to a gate of the transistor, the first voltage being a selected voltage, and the second voltage being a non-selected voltage, a voltage difference between the first voltage and the second voltage is larger than a voltage difference between a power supply voltage and a ground voltage, and one of the ground voltage and the power supply voltage which is closer to the non-selected voltage is applied to a back gate of the transistor irrespective of selection or non-selection.

    摘要翻译： 根据本发明的一个方面的半导体存储装置包括：DRAM单元，包括一个晶体管和一个电容器，其中第一电压和第二电压中的一个施加到晶体管的栅极，第一电压是选定的电压 ，第二电压为非选择电压时，第一电压与第二电压之间的电压差大于电源电压与接地电压之间的电压差，接地电压和电源电压之一 更接近于非选择电压的电压施加到晶体管的背栅极，而与选择或非选择无关。