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1.发明授权公开(公告)号：US07145812B2
公开(公告)日：2006-12-05
申请号：US11133974
申请日：2005-05-20
CPC分类号： G11C7/1045
摘要： There is provided a method of entry of an operation mode of a semiconductor memory during operations without need of any specific timing specification and with effective suppression to any erroneous entry.If read cycles for plural addresses are continued, then a request for entry of operation mode is accepted (steps S1 and S2). In write cycles following to those read cycles, an operation mode to be entered is decided based on data externally designated, wherein in the first write cycle, the kind of the operation mode is set, and then in the next write cycle, conditions for the operation mode are set for the entry of the operation mode of the semiconductor memory.
摘要翻译： 提供了一种在操作期间输入半导体存储器的操作模式的方法，而不需要任何特定的时序指定并有效抑制任何错误的输入。 如果持续多个地址的读取周期，则接受进入操作模式的请求（步骤S1和S2）。 在这些读取周期之后的写入周期中，基于外部指定的数据来决定要输入的操作模式，其中在第一写入周期中，设置操作模式的种类，然后在下一个写入周期中， 操作模式被设置用于输入半导体存储器的操作模式。
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公开(公告)号：US06925016B2
公开(公告)日：2005-08-02
申请号：US10467031
申请日：2002-01-30
IPC分类号： G11C11/401 , G11C7/10 , G11C11/403 , G11C11/406 , G11C7/00
CPC分类号： G11C7/1045
摘要： There is provided a method of entry of an operation mode of a semiconductor memory during operations without need of any specific timing specification and with effective suppression to any erroneous entry. If read cycles for plural addresses are continued, then, a request for entry of operation mode is accepted. In write cycles following to those read cycles, an operation mode to be entered is decided based on data externally designated, wherein in the first write cycle, the kind of the operation mode is set, and then in the next write cycle, conditions for the operation mode are set for the entry of the operation mode of the semiconductor memory.
摘要翻译： 提供了一种在操作期间输入半导体存储器的操作模式的方法，而不需要任何特定的时序指定并有效抑制任何错误的输入。 如果持续多个地址的读取周期，则接受进入操作模式的请求。 在这些读取周期之后的写入周期中，基于外部指定的数据来决定要输入的操作模式，其中在第一写入周期中，设置操作模式的种类，然后在下一个写入周期中， 操作模式被设置用于输入半导体存储器的操作模式。
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公开(公告)号：US06751144B2
公开(公告)日：2004-06-15
申请号：US10148430
申请日：2002-05-29
IPC分类号： G11C700
CPC分类号： G11C11/40615 , G11C8/18 , G11C11/406 , G11C29/12
摘要： A semiconductor storage having the same memory cells as a DRAM, operating in SRAM specifications, and having advantages such as a small chop size, a low power consumption, a low manufacturing cost, no access delay due to skew, and no memory cell breakdown. An ATD circuit (3) generates a one-shot pulse added to an address change detection signal (ATD) from a change of the address (Address) supplied from external. By combining one-shot pulse produced for each bit of the address, only one one-shot pulse is generated even if the address includes skew. A memory cell is refreshed by using a refresh address (R_ADD) generated by a refresh control circuit (4) during the time when a one-shot pulse is generated. At the fall of the one-shot pulse, a latch control signal (LC) is generated, and the address is taken in a latch (2) so as to access a memory cell array (6).
摘要翻译： 具有与DRAM相同的存储单元的半导体存储器，以SRAM规格工作，具有小斩尺寸，低功耗，低制造成本，无偏移的访问延迟以及无存储器单元故障等优点。 ATD电路（3）根据从外部提供的地址（地址）的改变产生添加到地址变化检测信号（ATD）的单触发脉冲。 通过组合为地址的每个位产生的单触发脉冲，即使地址包含偏斜，也只产生一个单触发脉冲。 通过使用在产生单次脉冲的时间期间由刷新控制电路（4）产生的刷新地址（R_ADD）来刷新存储器单元。 在单触发脉冲的下降时，产生锁存控制信号（LC），并将该地址取入锁存器（2），以访问存储单元阵列（6）。
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4.发明申请公开(公告)号：US20050216676A1
公开(公告)日：2005-09-29
申请号：US11133974
申请日：2005-05-20
IPC分类号： G11C11/401 , G11C7/10 , G11C11/403 , G11C11/406 , G06F13/00
CPC分类号： G11C7/1045
摘要： There is provided a method of entry of an operation mode of a semiconductor memory during operations without need of any specific timing specification and with effective suppression to any erroneous entry. If read cycles for plural addresses are continued, then a request for entry of operation mode is accepted (steps S1 and S2). In write cycles following to those read cycles, an operation mode to be entered is decided based on data externally designated, wherein in the first write cycle, the kind of the operation mode is set, and then in the next write cycle, conditions for the operation mode are set for the entry of the operation mode of the semiconductor memory.
摘要翻译： 提供了一种在操作期间输入半导体存储器的操作模式的方法，而不需要任何特定的时序指定并有效抑制任何错误的输入。 如果持续多个地址的读取周期，则接受进入操作模式的请求（步骤S1和S2）。 在这些读取周期之后的写入周期中，基于外部指定的数据来决定要输入的操作模式，其中在第一写入周期中，设置操作模式的种类，然后在下一个写入周期中， 操作模式被设置用于输入半导体存储器的操作模式。
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公开(公告)号：US06813212B2
公开(公告)日：2004-11-02
申请号：US10450276
申请日：2003-06-11
IPC分类号： G11C800
CPC分类号： G11C11/40615 , G11C11/406 , G11C2211/4067
摘要： Problems are prevented that a refresh provides an influence to a normal access and that a continuation of write operations inhibits refresh. In a semiconductor memory device, a clock signal providing a reference to a time interval of refresh operations based on addresses corresponding to a single row s generated as a refresh clock signal. A transition of an access address “Address” externally supplied and corresponding to a memory cell is detected, so that a refresh operation is executed to a memory cell corresponding to a refresh address by triggering the generation of this detection signal before an access to a memory cell designated by the access address is made, wherein the upon input of a write enable signal /WE, the refresh is executed by triggering this signal before a write operation is executed and the refresh operation by triggering the generation of the access address is discontinued in a predetermined period of time based on the refresh clock signal.
摘要翻译： 防止刷新对正常访问产生影响并且写入操作的继续禁止刷新的问题。 在半导体存储器件中，提供基于对应于作为刷新时钟信号生成的单行s的地址的刷新操作的时间间隔的时钟信号。 检测外部提供并对应于存储器单元的访问地址“地址”的转换，从而通过在访问存储器之前触发该检测信号的产生来对与刷新地址相对应的存储单元执行刷新操作 进行由访问地址指定的单元，其中，通过输入写入使能信号/ WE，在执行写入操作之前触发该信号来执行刷新，并且通过触发生成访问地址的刷新操作被中断 基于刷新时钟信号的预定时间段。
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6.发明申请Eye image pickup apparatus, iris authentication apparatus and portable terminal device having iris authentication function 失效眼睛摄像装置，虹膜认证装置和具有虹膜认证功能的便携式终端装置公开(公告)号：US20060120707A1
公开(公告)日：2006-06-08
申请号：US10400835
申请日：2003-03-27
申请人： Takashi Kusakari , Jyoji Wada , Tamotsu Kaneko
发明人： Takashi Kusakari , Jyoji Wada , Tamotsu Kaneko
IPC分类号： A61B3/14
CPC分类号： A61B5/1171 , A61B3/145 , A61B5/117 , G06K9/00604 , G07C9/00087 , G07C2009/00095 , H04L63/0861 , H04M2250/52 , H04W12/06 , H04W88/02
摘要： An iris authentication apparatus includes a camera for obtaining the image of an eye; a display panel arranged on the same plane as where the lens of the camera is arranged; and guide character generation means, wherein a guide character is displayed on a display panel, and the eye of a person to be authenticated who watches the guide character is guided. As a result, a satisfactory iris image can be obtained by the iris authentication apparatus of one camera type that does not have a zooming function, so that the iris authentication apparatus that can be mounted to a small body, such as a portable telephone, can be provided.
摘要翻译： 虹膜认证装置包括用于获得眼睛图像的照相机; 布置在相机的透镜相同平面上的显示面板; 以及引导字符生成单元，其中，在显示面板上显示引导字符，并且引导观看指导人物的要认证的人的眼睛。 结果，可以通过不具有缩放功能的一种摄像机类型的虹膜认证装置获得令人满意的虹膜图像，使得可以安装到诸如便携式电话的小身体的虹膜认证装置可以 提供。
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公开(公告)号：US20100220987A1
公开(公告)日：2010-09-02
申请号：US11997507
申请日：2006-07-14
申请人： Akihiko Kato , Norihiko Kikuchi , Takashi Kusakari
发明人： Akihiko Kato , Norihiko Kikuchi , Takashi Kusakari
IPC分类号： G03B3/10
CPC分类号： G02B7/08 , H04N5/23212
摘要： It is an object of the present invention to provide an imaging device that can be reduced in production cost in comparison with the conventional imaging device, and a portable terminal provided with the imaging device. The imaging device 10 comprises a lens 11 for focusing light from an object, a magnet 12 attached to the lens 11, lens moving means 13 for moving the lens 11 along an optical axis of the lens 11, a hall element 14 for detecting a magnetic flax generated by the magnet 12, a constant current circuit 15 for driving the hall element 14, an amplifier 16 for amplifying an output voltage of the hall element 14, a comparator 17 for comparing a reference voltage with the output voltage of the hall element 14, a PWM signal producing unit 18 for producing a pulse width modulation signal, a lens controller 19 for outputting a control signal to the lens moving means 13 to control the lens moving means 13, and a lens driver 20 for driving the lens moving means 13.
摘要翻译： 本发明的目的是提供一种与传统的成像装置相比可以降低制造成本的成像装置，以及设置有成像装置的便携式终端。 成像装置10包括用于聚焦来自物体的光的透镜11，附接到透镜11的磁体12，用于沿着透镜11的光轴移动透镜11的透镜移动装置13，用于检测磁性的霍尔元件14 由磁体12产生的亚麻，用于驱动霍尔元件14的恒流电路15，放大霍尔元件14的输出电压的放大器16，将参考电压与霍尔元件14的输出电压进行比较的比较器17 ，用于产生脉宽调制信号的PWM信号产生单元18，用于向透镜移动装置13输出控制信号以控制透镜移动装置13的透镜控制器19和用于驱动透镜移动装置13的透镜驱动器20 。
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公开(公告)号：US5432743A
公开(公告)日：1995-07-11
申请号：US84016
申请日：1993-06-30
申请人： Takashi Kusakari
发明人： Takashi Kusakari
CPC分类号： G11C7/1006
摘要： A semiconductor dynamic RAM for image processing, according to the present invention, comprises a VRAM having logical operation function of performing a predetermined logical operation of an input data signal and an output from a selected one of memory cells and rewriting the selected memory cell with a result of the operation. It includes a write read control circuit including a level determination circuit for determining a level of the input signal under control of the logical operation enable signal. Based on the result of determination of the logical level of the input signal, either write of the input signal to the selected memory cell or refresh of information stored in the selected cell is performed to effectively perform the logical operation.
摘要翻译： 根据本发明的用于图像处理的半导体动态RAM包括具有执行输入数据信号的预定逻辑运算和来自所选择的一个存储单元的输出的逻辑运算功能的VRAM，并且用一个 操作结果。 它包括写入读取控制电路，该写入读取控制电路包括用于在逻辑运算使能信号的控制下确定输入信号的电平的电平确定电路。 基于确定输入信号的逻辑电平的结果，执行将输入信号写入所选存储单元或刷新存储在所选单元中的信息，以有效地执行逻辑运算。
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9.发明申请TRADE SUPPORT PROCESS SYSTEM, TRADE SUPPORT PROCESS METHOD, AND RECORDING MEDIUM 审中-公开贸易支持流程系统，贸易支持流程方法和记录介质公开(公告)号：US20090299892A1
公开(公告)日：2009-12-03
申请号：US12476459
申请日：2009-06-02
申请人： Hiroyuki Kasai , Eiichi Tezuka , Keisuke Sekiguchi , Shinya Kimoto , Yumi Yamamoto , Junko Yoshida , Yoshikazu Takita , Seiji Goto , Takashi Kusakari
发明人： Hiroyuki Kasai , Eiichi Tezuka , Keisuke Sekiguchi , Shinya Kimoto , Yumi Yamamoto , Junko Yoshida , Yoshikazu Takita , Seiji Goto , Takashi Kusakari
IPC分类号： G06Q40/00
摘要： Receipt of an order for a support for transportation in a trade or for documentation in a trade is managed. A control unit of a service management server sends an order receipt information registration screen. In a case where a service pattern is selected on the order receipt information registration screen, the control unit retrieves service plans that constitute the service pattern, and outputs the service plans. Then, the control unit acquires order receipt particulars information about the service plans. Then, the control unit registers order receipt management data. On the other hand, in a case where order receipt information is input in the order receipt information registration screen, the control unit retrieves a service plan that matches the order receipt information, and outputs the service plan.
摘要翻译： 管理交易中的运输支持订单或交易文件的收货。 服务管理服务器的控制单元发送订单收据信息登记画面。 在订单收据信息登记画面上选择服务模式的情况下，控制部检索构成服务模式的服务计划，并输出服务计划。 然后，控制单元获取关于服务计划的订单接收细节信息。 然后，控制单元登记订单收据管理数据。 另一方面，在订单收据信息登记画面中输入订单收据信息的情况下，控制部检索与订单收据信息相匹配的服务计划，并输出服务计划。
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10.发明授权Method of flash writing with small operation current and semiconductor memory circuit according to the method 失效根据该方法，使用小操作电流的闪存写入方法和半导体存储器电路
公开(公告)号：US5473565A
公开(公告)日：1995-12-05
申请号：US300190
申请日：1994-09-02
申请人： Takashi Kusakari
发明人： Takashi Kusakari
IPC分类号： G11C11/409 , G11C7/20 , G11C7/22 , G11C11/401 , G11C7/00
摘要： The present invention provides a semiconductor memory circuit which can restrict the increase of an operation current in a flash write mode to a minimum even when there are problems caused in the manufacturing process such as short-circuits in the wiring. A timing control circuit of the semiconductor memory circuit of the present invention comprises an FW latch signal generation circuit and a latch circuit both for detecting that a row address strobe signal, an RAS signal and a flash write enable signal inputted have become active, and an FW gate signal generation circuit for activating the FW gate signal for only a limited fixed time determined by a delay circuit when an FW gate activation signal is outputted from the latch circuit which has detected the activation of both signals. With the FW gate signal activated, the flash write gate switch turns active for performing the flash write activity. After the flash write activity is finished, the FW gate signal becomes inactive immediately even when the RAS signal is active.
摘要翻译： 本发明提供了一种半导体存储器电路，其即使在制造过程中引起诸如布线短路的问题，也可以将闪光写入模式中的工作电流的增加限制到最小。 本发明的半导体存储电路的定时控制电路包括一个FW锁存信号产生电路和一个锁存电路，用于检测输入的行地址选通信号，＆upbar＆R信号和闪速写入使能信号是否变为有效，以及 FW门信号发生电路，用于当从检测到两个信号的激活的锁存电路输出FW门激活信号时，仅在由延迟电路确定的有限固定时间内激活FW门信号。 激活FW门信号时，闪存写入开关变为有效，用于执行闪存写入活动。 闪存写入动作完成后，即使“upbar＆R”信号有效，FW门控信号立即变为无效。
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