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公开(公告)号：US06751144B2
公开(公告)日：2004-06-15
申请号：US10148430
申请日：2002-05-29
IPC分类号： G11C700
CPC分类号： G11C11/40615 , G11C8/18 , G11C11/406 , G11C29/12
摘要： A semiconductor storage having the same memory cells as a DRAM, operating in SRAM specifications, and having advantages such as a small chop size, a low power consumption, a low manufacturing cost, no access delay due to skew, and no memory cell breakdown. An ATD circuit (3) generates a one-shot pulse added to an address change detection signal (ATD) from a change of the address (Address) supplied from external. By combining one-shot pulse produced for each bit of the address, only one one-shot pulse is generated even if the address includes skew. A memory cell is refreshed by using a refresh address (R_ADD) generated by a refresh control circuit (4) during the time when a one-shot pulse is generated. At the fall of the one-shot pulse, a latch control signal (LC) is generated, and the address is taken in a latch (2) so as to access a memory cell array (6).
摘要翻译： 具有与DRAM相同的存储单元的半导体存储器，以SRAM规格工作，具有小斩尺寸，低功耗，低制造成本，无偏移的访问延迟以及无存储器单元故障等优点。 ATD电路（3）根据从外部提供的地址（地址）的改变产生添加到地址变化检测信号（ATD）的单触发脉冲。 通过组合为地址的每个位产生的单触发脉冲，即使地址包含偏斜，也只产生一个单触发脉冲。 通过使用在产生单次脉冲的时间期间由刷新控制电路（4）产生的刷新地址（R_ADD）来刷新存储器单元。 在单触发脉冲的下降时，产生锁存控制信号（LC），并将该地址取入锁存器（2），以访问存储单元阵列（6）。
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2.发明授权公开(公告)号：US07145812B2
公开(公告)日：2006-12-05
申请号：US11133974
申请日：2005-05-20
CPC分类号： G11C7/1045
摘要： There is provided a method of entry of an operation mode of a semiconductor memory during operations without need of any specific timing specification and with effective suppression to any erroneous entry.If read cycles for plural addresses are continued, then a request for entry of operation mode is accepted (steps S1 and S2). In write cycles following to those read cycles, an operation mode to be entered is decided based on data externally designated, wherein in the first write cycle, the kind of the operation mode is set, and then in the next write cycle, conditions for the operation mode are set for the entry of the operation mode of the semiconductor memory.
摘要翻译： 提供了一种在操作期间输入半导体存储器的操作模式的方法，而不需要任何特定的时序指定并有效抑制任何错误的输入。 如果持续多个地址的读取周期，则接受进入操作模式的请求（步骤S1和S2）。 在这些读取周期之后的写入周期中，基于外部指定的数据来决定要输入的操作模式，其中在第一写入周期中，设置操作模式的种类，然后在下一个写入周期中， 操作模式被设置用于输入半导体存储器的操作模式。
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公开(公告)号：US06925016B2
公开(公告)日：2005-08-02
申请号：US10467031
申请日：2002-01-30
IPC分类号： G11C11/401 , G11C7/10 , G11C11/403 , G11C11/406 , G11C7/00
CPC分类号： G11C7/1045
摘要： There is provided a method of entry of an operation mode of a semiconductor memory during operations without need of any specific timing specification and with effective suppression to any erroneous entry. If read cycles for plural addresses are continued, then, a request for entry of operation mode is accepted. In write cycles following to those read cycles, an operation mode to be entered is decided based on data externally designated, wherein in the first write cycle, the kind of the operation mode is set, and then in the next write cycle, conditions for the operation mode are set for the entry of the operation mode of the semiconductor memory.
摘要翻译： 提供了一种在操作期间输入半导体存储器的操作模式的方法，而不需要任何特定的时序指定并有效抑制任何错误的输入。 如果持续多个地址的读取周期，则接受进入操作模式的请求。 在这些读取周期之后的写入周期中，基于外部指定的数据来决定要输入的操作模式，其中在第一写入周期中，设置操作模式的种类，然后在下一个写入周期中， 操作模式被设置用于输入半导体存储器的操作模式。
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4.发明申请公开(公告)号：US20050216676A1
公开(公告)日：2005-09-29
申请号：US11133974
申请日：2005-05-20
IPC分类号： G11C11/401 , G11C7/10 , G11C11/403 , G11C11/406 , G06F13/00
CPC分类号： G11C7/1045
摘要： There is provided a method of entry of an operation mode of a semiconductor memory during operations without need of any specific timing specification and with effective suppression to any erroneous entry. If read cycles for plural addresses are continued, then a request for entry of operation mode is accepted (steps S1 and S2). In write cycles following to those read cycles, an operation mode to be entered is decided based on data externally designated, wherein in the first write cycle, the kind of the operation mode is set, and then in the next write cycle, conditions for the operation mode are set for the entry of the operation mode of the semiconductor memory.
摘要翻译： 提供了一种在操作期间输入半导体存储器的操作模式的方法，而不需要任何特定的时序指定并有效抑制任何错误的输入。 如果持续多个地址的读取周期，则接受进入操作模式的请求（步骤S1和S2）。 在这些读取周期之后的写入周期中，基于外部指定的数据来决定要输入的操作模式，其中在第一写入周期中，设置操作模式的种类，然后在下一个写入周期中， 操作模式被设置用于输入半导体存储器的操作模式。
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公开(公告)号：US06813212B2
公开(公告)日：2004-11-02
申请号：US10450276
申请日：2003-06-11
IPC分类号： G11C800
CPC分类号： G11C11/40615 , G11C11/406 , G11C2211/4067
摘要： Problems are prevented that a refresh provides an influence to a normal access and that a continuation of write operations inhibits refresh. In a semiconductor memory device, a clock signal providing a reference to a time interval of refresh operations based on addresses corresponding to a single row s generated as a refresh clock signal. A transition of an access address “Address” externally supplied and corresponding to a memory cell is detected, so that a refresh operation is executed to a memory cell corresponding to a refresh address by triggering the generation of this detection signal before an access to a memory cell designated by the access address is made, wherein the upon input of a write enable signal /WE, the refresh is executed by triggering this signal before a write operation is executed and the refresh operation by triggering the generation of the access address is discontinued in a predetermined period of time based on the refresh clock signal.
摘要翻译： 防止刷新对正常访问产生影响并且写入操作的继续禁止刷新的问题。 在半导体存储器件中，提供基于对应于作为刷新时钟信号生成的单行s的地址的刷新操作的时间间隔的时钟信号。 检测外部提供并对应于存储器单元的访问地址“地址”的转换，从而通过在访问存储器之前触发该检测信号的产生来对与刷新地址相对应的存储单元执行刷新操作 进行由访问地址指定的单元，其中，通过输入写入使能信号/ WE，在执行写入操作之前触发该信号来执行刷新，并且通过触发生成访问地址的刷新操作被中断 基于刷新时钟信号的预定时间段。
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6.发明授权Semiconductor memory device for preventing a late write from disturbing a refresh operation 有权半导体存储装置，用于防止后期写入干扰刷新操作公开(公告)号：US07089351B2
公开(公告)日：2006-08-08
申请号：US10479635
申请日：2002-05-28
IPC分类号： G06F12/16
CPC分类号： G11C11/40603 , G11C11/406 , G11C11/40615 , G11C2211/4067
摘要： A semiconductor memory device is provided for preventing a late-write from disturbing a refresh operation and also for reducing a current consumption in a write cycle with execution of the late-write. Upon a transition of an address ADD, an address transition detector circuit detects this address transition. Upon receipt of a result of detection by the address transition detector circuit, a state control circuit judges an operation to be executed, from an output enable signal /OE and a write enable signal /WE, and then outputs any of a read statement RS, a write statement WS, and a refresh statement FS. According to a clock signal ACLK, input signals such as addresses are taken for executions of operations based on the statements.
摘要翻译： 提供一种半导体存储器件，用于防止后期写入干扰刷新操作，并且还用于通过执行后期写入来减少写周期中的电流消耗。 地址转换检测器电路在地址ADD的转换时检测该地址转换。 一旦状态控制电路接收到由地址转换检测器电路检测到的结果，就从输出使能信号/ OE和写使能信号/ WE判断要执行的操作，然后输出读出的语句RS， 写入语句WS和刷新语句FS。 根据时钟信号ACLK，基于语句执行诸如地址的输入信号来执行操作。
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公开(公告)号：US20050047239A1
公开(公告)日：2005-03-03
申请号：US10500400
申请日：2002-12-25
申请人： Hiroyuki Takahashi , Takuya Hirota , Noriaki Komatsu , Atsushi Nakagawa , Susumu Takano , Masahiro Yoshida , Yuuji Torige , Hideo Inaba
发明人： Hiroyuki Takahashi , Takuya Hirota , Noriaki Komatsu , Atsushi Nakagawa , Susumu Takano , Masahiro Yoshida , Yuuji Torige , Hideo Inaba
IPC分类号： G11C11/403 , G11C11/406 , G11C7/00
CPC分类号： G11C11/40603 , G11C11/406
摘要： Refresh of memory cells is performed periodically by a refresh timer, and collision between memory access and memory refresh is avoided. When memory access occurs, an F/F 163 is set by a one shot pulse from an OS circuit 161, a memory access request is inputted to a memory accessing pulse generator circuit 171 through a NOR gate 167, and a latch control signal LC and an enable signal REN are outputted. When a refresh request from the refresh timer is inputted to an AND gate 168 during the memory access, the output of the NOR gate 167 is at the “L” level, and the refresh request is blocked by the AND gate 168. Thereafter, at the time when the latch control signal LC is turned into the “L” level, F/Fs 163, 164 and 165 are reset, the output of the NOR gate 167 is turned into the “H” level, the refresh request is inputted to a refreshing pulse generator circuit 170, and a refresh enable signal RERF is outputted.
摘要翻译： 通过刷新定时器周期性地执行存储器单元的刷新，并避免存储器访问和存储器刷新之间的冲突。 当存储器访问发生时，通过来自OS电路161的单触发脉冲设置F / F 163，通过NOR门167将存储器访问请求输入到存储器访问脉冲发生器电路171，以及锁存控制信号LC和 输出使能信号REN。 当在存储器访问期间来自刷新定时器的刷新请求被输入到与门168时，或非门167的输出处于“L”电平，刷新请求由与门168阻止。此后， 当锁存控制信号LC变为“L”电平时，F / F 163,164和165被复位，或非门167的输出变成“H”电平，刷新请求被输入到 输出刷新脉冲发生器电路170和刷新使能信号RERF。
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公开(公告)号：US06646956B2
公开(公告)日：2003-11-11
申请号：US10221249
申请日：2002-09-10
IPC分类号： G11C800
CPC分类号： H03K5/1534 , G11C8/18 , H03K2005/00293
摘要： A one-shot signal generation circuit is provided which makes it easy to adjust pulse width and to deal with variation of skew of an ATD signal, and can reduce chip area. A timing determination section (100) is reset by an edge of a first detected signal among a plurality of address transition detection signals (ATD signals) which have arrived within the skew period of an address signal, measures a first predetermined time by taking an edge of a second detected signal as start instant, and outputs a signal DST which reflects the result of this measurement. A timing determination section (110) measures a second predetermined time by taking an edge of the first detected signal as start instant, and outputs a signal PG which reflects the result of this measurement. An LC generation circuit (14) outputs a one-shot signal (LC) whose start instant is determined by the signal PG and whose end instant is determined by the signal DST.
摘要翻译： 提供了一个单触发信号发生电路，可以方便的调整脉冲宽度并应对ATD信号的偏斜变化，并可以减少芯片面积。 定时确定部分（100）由在地址信号的歪斜时段内到达的多个地址转换检测信号（ATD信号）中的第一检测信号的边沿复位，通过取边缘来测量第一预定时间 的第二检测信号作为开始时刻，并且输出反映该测量结果的信号DST。 定时确定部分（110）通过将第一检测信号的边缘作为开始时刻来测量第二预定时间，并且输出反映该测量结果的信号PG。 LC生成电路（14）输出由信号PG确定开始时刻的单触发信号（LC），并且由信号DST确定其结束时刻。
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9.发明授权公开(公告)号：US07054224B2
公开(公告)日：2006-05-30
申请号：US10478369
申请日：2002-05-23
IPC分类号： G11C8/00
CPC分类号： G11C11/40615 , G11C7/1012 , G11C7/1051 , G11C11/406 , G11C11/4096
摘要： The present invention provides a non-synchronous semiconductor memory device configured as a pseudo-SRAM and capable of relaxing the limitation to address skew and improving the read rate. A data latch circuit 110 holds data having been read out of memory cells in a memory cell array 106 designated by a tow address included in an address ADD in a read mode. Upon transitions of column addresses A0, A1 included in the address, a multiplexer 111 sequentially and non-synchronously feeds out the data held in the data latch circuit 110 based on the column addresses A0, A1.
摘要翻译： 本发明提供一种被配置为伪SRAM的非同步半导体存储器件，并且能够放宽对寻址偏移的限制并提高读取速率。 数据锁存电路110将从存储单元读出的数据保存在由读取模式中包含在地址ADD中的拖尾地址指定的存储单元阵列106中。 在地址中包括的列地址A 0，A 1的转换中，多路复用器111基于列地址A 0，A 1顺序地并且不同步地馈送保存在数据锁存电路110中的数据。
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10.发明申请Semiconductor storage device, test method therefor, and test circuit therefor 失效半导体存储装置及其测试方法及其测试电路公开(公告)号：US20050207252A1
公开(公告)日：2005-09-22
申请号：US10498398
申请日：2002-12-10
申请人： Hiroyuki Takahashi , Hideo Inaba , Syouzou Uchida
发明人： Hiroyuki Takahashi , Hideo Inaba , Syouzou Uchida
IPC分类号： G01R31/28 , G01R31/3185 , G11C8/18 , G11C11/401 , G11C11/403 , G11C11/406 , G11C29/08 , G11C29/14 , G11C7/00
CPC分类号： G11C29/12015 , G11C8/18 , G11C11/401 , G11C11/406 , G11C29/14
摘要： A test method and a test circuit which enable operations to be checked when the time interval between a refresh operation and a read or write operation is forcibly reduced. Timings for a read or write operation in a normal operation mode and in a test mode are determined on the basis of an address transition detection circuit. A timing for a refresh operation in the normal operation mode is set on the basis of a normal refreshing pulse signal generated by a refresh pulse generating circuit in response to a timing signal generated by a timer circuit. A timing for a refresh operation in the test mode is set on the basis of a first testing refresh pulse generation signal generated by a first testing refresh pulse generating circuit in response to the address transition detection signal. By controlling a timing for generating the first testing refresh pulse generation signal, it is possible to generate a read or write operation and a refresh operation so that there is a predetermined time interval between these operations.
摘要翻译： 当刷新操作和读/写操作之间的时间间隔被强制降低时，能够检查操作的测试方法和测试电路。 基于地址转换检测电路来确定在正常操作模式和测试模式下进行读或写操作的时序。 基于由定时器电路产生的定时信号由刷新脉冲发生电路产生的正常刷新脉冲信号来设定正常操作模式下的刷新操作的定时。 基于由第一测试刷新脉冲发生电路响应于地址转换检测信号产生的第一测试刷新脉冲产生信号来设置测试模式下的刷新操作的定时。 通过控制用于产生第一测试刷新脉冲产生信号的定时，可以产生读或写操作和刷新操作，使得在这些操作之间存在预定的时间间隔。
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