Increased reliability in the processing of digital signals
    1.
    发明授权
    Increased reliability in the processing of digital signals 有权
    提高数字信号处理的可靠性

    公开(公告)号:US08738331B2

    公开(公告)日:2014-05-27

    申请号:US12663375

    申请日:2008-06-04

    IPC分类号: H04B15/04

    摘要: A method, device and computer program product for providing increased reliability in the processing of digital signals. The device includes a module for performing analog measurement of a received signal intended to occupy two logical states at various instances in time, a module for determining if there is a change in the analog signal level, a module for determining if the change fulfills at least one logical state change condition, wherein a first logical state change condition is based on the speed of change of the analog signal level, and a module for determining that there is a change from one logical state to the other if at least one logical state change condition is fulfilled. The invention provides secure detection of unreliable digital signals that may be generated in harsh environments that are polluted or moist.

    摘要翻译: 一种用于在数字信号的处理中提供增加的可靠性的方法,装置和计算机程序产品。 该装置包括一个模块,用于对在时间上各种不同情况下占用两个逻辑状态的接收信号进行模拟测量,模块,用于确定模拟信号电平是否有变化;模块,用于确定变化是否至少满足 一个逻辑状态改变条件,其中第一逻辑状态改变条件基于模拟信号电平的变化速度,以及用于确定如果至少一个逻辑状态改变则存在从一个逻辑状态到另一个逻辑状态的改变的模块 条件得到满足。 本发明提供对可能在被污染或潮湿的恶劣环境中产生的不可靠数字信号的安全检测。

    Method and apparatus for measuring settling characteristics of a device
under test by using a measurement system for measuring an input signal
by sampling and digitizing said input signal
    2.
    发明授权
    Method and apparatus for measuring settling characteristics of a device under test by using a measurement system for measuring an input signal by sampling and digitizing said input signal 失效
    通过使用测量系统来测量被测设备的稳定特性的方法和装置,用于通过采样和数字化所述输入信号来测量输入信号

    公开(公告)号:US4833403A

    公开(公告)日:1989-05-23

    申请号:US104883

    申请日:1987-10-05

    CPC分类号: G01R29/0276

    摘要: A method and an apparatus for measuring settling characteristics of a device under test. A measurement system for measuring an input signal by sampling and digitizing that input signal is employed to obtain reference data by measuring a reference signal, at least one level of which is flat, and to obtain measurement data by measuring a second signal representing the settling characteristics to be measured but containing an error component due to inclusion of the measurement system itself. The error component is removed from the measurement data by adjusting the timing and level of the reference data relative to those of the measurement data.

    摘要翻译: 一种用于测量被测设备的沉降特性的方法和装置。 采用通过对该输入信号进行采样和数字化来测量输入信号的测量系统,通过测量其至少一个电平是平坦的参考信号来获得参考数据,并且通过测量表示稳定特性的第二信号来获得测量数据 被测量但由于包含测量系统本身而包含误差分量。 通过调整参考数据的时间和电平相对于测量数据的时间和电平,从测量数据中去除误差分量。

    Method For Arc Detection And Devices Thereof
    4.
    发明申请
    Method For Arc Detection And Devices Thereof 审中-公开
    电弧检测方法及其设备

    公开(公告)号:US20120280717A1

    公开(公告)日:2012-11-08

    申请号:US13515159

    申请日:2009-12-11

    申请人: Junhua Fu

    发明人: Junhua Fu

    IPC分类号: G01R29/02

    摘要: A method for arc detection includes detecting a changing rate of a signal indicative of light strength, detecting the amplitude of the signal, and indicating an occurrence of an arc if the changing rate of the signal exceeds a first predetermined threshold and the amplitude of the signal exceeds a second predetermined threshold. An arc detecting device, an arc detecting system, and an arc protecting apparatus thereof are provided. The arc detecting system includes a light collector (101) for collecting light, a light converter (103) coupled to the light collector (101) for converting the collected light into an electric signal, and an arc detecting device (106) coupled to the light converter (103) for detecting the occurrence of the arc. The arc detecting device (106) comprises a slope criterion module configured to determine if the changing rate of the signal indicative of the light strength exceeds the first predetermined threshold and an absolute value criterion module configured to determine if the amplitude of the signal exceeds the second predetermined threshold.

    摘要翻译: 一种用于电弧检测的方法包括检测指示光强度的信号的变化率,检测信号的幅度,以及如果信号的变化率超过第一预定阈值并且信号的幅度,则指示电弧的出现 超过第二预定阈值。 提供了一种电弧检测装置,电弧检测系统及其电弧保护装置。 电弧检测系统包括用于收集光的集光器(101),耦合到集光器(101)的光转换器(103),用于将收集的光转换成电信号;以及电弧检测装置(106),耦合到 光转换器(103),用于检测电弧的发生。 电弧检测装置(106)包括倾斜标准模块,其被配置为确定指示光强度的信号的变化率是否超过第一预定阈值,绝对值标准模块被配置为确定信号的幅度是否超过第二 预定阈值。

    Test circuit for evaluating characteristic of analog signal of device
    5.
    发明授权
    Test circuit for evaluating characteristic of analog signal of device 失效
    用于评估设备模拟信号特性的测试电路

    公开(公告)号:US07079060B2

    公开(公告)日:2006-07-18

    申请号:US11048723

    申请日:2005-02-03

    IPC分类号: H03M1/12

    摘要: In a test circuit, a determination circuit conducts a function test to determine whether timing of a slope section of waveform of an analog signal ANS of a measurement target device is within a range of specifications. An ADC performs AD-conversion only when a potential of analog signal ANS is within a range between reference potentials VOL, VOH. An analysis unit analyzes digital data from the ADC, and conducts a sloping waveform test to evaluate a sloping state of the waveform of analog signal ANS. Therefore, the slope section of the waveform of analog signal ANS of the device can be subjected to AD-conversion in a voltage range divided in arbitrary number of sections within a range of arbitrary voltage amplitude without requiring a large-capacity storage circuit. The function test by a determination circuit and the sloping waveform test by the analysis unit can be performed in parallel.

    摘要翻译: 在测试电路中,确定电路进行功能测试,以确定测量目标器件的模拟信号ANS的波形的斜率部分的定时是否在规格范围内。 只有当模拟信号ANS的电位在参考电位VOL,VOH之间的范围内时,ADC才执行AD转换。 分析单元从ADC分析数字数据,并进行倾斜波形测试,以评估模拟信号ANS波形的倾斜状态。 因此,可以在不需要大容量存储电路的情况下,在任意电压幅度的范围内,以任意数量的区间划分的装置的模拟信号ANS的波形的斜率部分进行AD转换。 可以并行地执行由判定电路进行的功能测试和分析单元的倾斜波形测试。

    Overvoltage-pulse analyzer
    6.
    发明授权
    Overvoltage-pulse analyzer 失效
    过压脉冲分析仪

    公开(公告)号:US4365193A

    公开(公告)日:1982-12-21

    申请号:US174695

    申请日:1980-08-01

    摘要: A system for measuring and storing the amplitudes plus duration and/or rise times of overvoltage pulses occurring on a transmission line comprises a voltage divider working into a first and a second comparator respectively detecting an abnormal voltage exceeding a predetermined sensitivity threshold and discriminating among different amplitude levels above that threshold. The first comparator triggers an oscillator driving a pulse counter which measures the duration of an overvoltage pulse and also provides quantized information on rise time to the highest amplitude threshold surpassed by that pulse as determined by the second comparator. This information is stored in a memory with two groups of cells respectively assigned to combinations of amplitude with duration and combinations of amplitude with rise time, the occurrence of any such combination incrementing the contents of the respective cell. These cells are cyclically scannable and their contents can be selectively displayed on a visualizer such as an oscilloscope.

    摘要翻译: 用于测量和存储幅度加上在传输线上发生的过电压脉冲的持续时间和/或上升时间的系统包括分压器,分压器分别工作在第一和第二比较器中,分别检测超过预定灵敏度阈值的异常电压,并在不同幅度 高于该阈值。 第一比较器触发振荡器驱动脉冲计数器,该脉冲计数器测量过电压脉冲的持续时间,并且还将上升时间的量化信息提供给由第二比较器确定的该脉冲超过的最大幅度阈值。 该信息被存储在具有两组信元的存储器中,这两组信元分别被分配给具有持续时间的幅度和振幅的组合与上升时间的组合,任何这样的组合的出现增加了相应单元的内容。 这些单元是循环可扫描的,并且它们的内容可以有选择地显示在诸如示波器的可视化器上。

    Circuit for measuring rising or falling time of high-speed data and method thereof
    7.
    发明申请
    Circuit for measuring rising or falling time of high-speed data and method thereof 审中-公开
    用于测量高速数据上升或下降时间的电路及其方法

    公开(公告)号:US20030187599A1

    公开(公告)日:2003-10-02

    申请号:US10315024

    申请日:2002-12-10

    IPC分类号: G06F019/00

    CPC分类号: G01R29/0276

    摘要: A circuit and a method for measuring rising or falling time of high-speed data are disclosed. The circuit includes a comparator and a storage circuit. The comparator receives the high-speed data via a first port and a reference signal via a second port, compares a level of the high-speed data with a level of the reference signal in response to an enable signal, and outputs the compared result as a signal. A reference signal generator generates the reference signal. An enable signal generator generates the enable signal. The storage circuit receives and stores the signal and measures the rising or falling time of the high-speed data.

    摘要翻译: 公开了一种用于测量高速数据的上升或下降时间的电路和方法。 电路包括比较器和存储电路。 比较器经由第一端口和参考信号经由第二端口接收高速数据,响应于使能信号将高速数据的电平与参考信号的电平进行比较,并将比较结果作为 一个信号。 参考信号发生器产生参考信号。 使能信号发生器产生使能信号。 存储电路接收并存储信号并测量高速数据的上升或下降时间。

    Timing signal generator
    9.
    发明授权
    Timing signal generator 失效
    定时信号发生器

    公开(公告)号:US4864160A

    公开(公告)日:1989-09-05

    申请号:US93438

    申请日:1987-09-04

    申请人: David G. Abdoo

    发明人: David G. Abdoo

    摘要: A timing generator for generating timing signals representing the leading and trailing edges of test pulses. In one embodiment of the invention, a period circuit repetitively measures time intervals, or periods, based on signals from a clock circuit, and a marker circuit generates timing signals representing leading edge and trailing edge markers precisely within each period. The period circuit comprises a period-end memory having a plurality of storage locations which are addressed by a modulo(n) counter. To support multiple timing sets, or timing cycles, one or more of the most significant bits of the address field for the period-end memory may be reserved for designating each timing signal. The time interval measured by the period-end memory may be selectively extended by delaying the clocking signal used for incrementing the modulo(n) counter. The marker circuit comprises leading edge and trailing edge marker memories for storing values indicating where in a period a leading edge or a trailing edge marker is generated. The marker circuit further comprises extended cycle leading edge and trailing edge marker memories for storing values indicating where in a later timing cycle a marker is to be generated. Leading edge and trailing edge marker vernier memories are provided for storing values used to indicate the exact placement of markers within the time interval. Leading edge and trailing edge end-of-cycle marker memories are used for generating leading edge and trailing edge markers at the end of a particular timing cycle. Leading edge and trailing edge marker inhibit memories are used for inhibiting marker generation within a particular timing cycle.

    摘要翻译: 定时发生器,用于产生表示测试脉冲的前沿和后沿的定时信号。 在本发明的一个实施例中,周期电路基于来自时钟电路的信号重复地测量时间间隔或周期,并且标记电路在每个周期内精确地产生表示前沿和后沿标记的定时信号。 周期电路包括具有由模(n)计数器寻址的多个存储位置的周期存储器。 为了支持多个时序集或定时周期,周期结束存储器的地址字段的一个或多个最高有效位可以被保留用于指定每个定时信号。 可以通过延迟用于递增模(n)计数器的时钟信号来选择性地扩展由周期存储器测量的时间间隔。 标记电路包括前沿和后沿标记存储器,用于存储指示在一个周期内在前沿或后沿标记产生的位置的值。 标记电路还包括扩展周期前沿和后沿标记存储器,用于存储指示在稍后的定时周期中将要生成标记的位置的值。 提供前沿和后沿标记游标存储器用于存储用于指示标记在时间间隔内的确切位置的值。 前沿和后沿循环结束标记存储器用于在特定定时周期结束时产生前沿和后沿标记。 前沿和后沿标记禁止存储器用于抑制特定定时周期内的标记生成。