摘要:
A method, device and computer program product for providing increased reliability in the processing of digital signals. The device includes a module for performing analog measurement of a received signal intended to occupy two logical states at various instances in time, a module for determining if there is a change in the analog signal level, a module for determining if the change fulfills at least one logical state change condition, wherein a first logical state change condition is based on the speed of change of the analog signal level, and a module for determining that there is a change from one logical state to the other if at least one logical state change condition is fulfilled. The invention provides secure detection of unreliable digital signals that may be generated in harsh environments that are polluted or moist.
摘要:
A method and an apparatus for measuring settling characteristics of a device under test. A measurement system for measuring an input signal by sampling and digitizing that input signal is employed to obtain reference data by measuring a reference signal, at least one level of which is flat, and to obtain measurement data by measuring a second signal representing the settling characteristics to be measured but containing an error component due to inclusion of the measurement system itself. The error component is removed from the measurement data by adjusting the timing and level of the reference data relative to those of the measurement data.
摘要:
A noise detection circuit includes a first transistor configured to receive a delayed version of a clock signal; a second transistor configured to receive a delayed version of a reference clock signal; and a latch circuit, coupled to the first transistor at a first node and coupled to the second transistor at a second node, and configured to latch logic states of voltage levels at the first and second nodes, respectively, based on whether a timing difference between transition edges of the clock signal and the reference clock signal exceeds a pre-defined timing offset threshold.
摘要:
A method for arc detection includes detecting a changing rate of a signal indicative of light strength, detecting the amplitude of the signal, and indicating an occurrence of an arc if the changing rate of the signal exceeds a first predetermined threshold and the amplitude of the signal exceeds a second predetermined threshold. An arc detecting device, an arc detecting system, and an arc protecting apparatus thereof are provided. The arc detecting system includes a light collector (101) for collecting light, a light converter (103) coupled to the light collector (101) for converting the collected light into an electric signal, and an arc detecting device (106) coupled to the light converter (103) for detecting the occurrence of the arc. The arc detecting device (106) comprises a slope criterion module configured to determine if the changing rate of the signal indicative of the light strength exceeds the first predetermined threshold and an absolute value criterion module configured to determine if the amplitude of the signal exceeds the second predetermined threshold.
摘要:
In a test circuit, a determination circuit conducts a function test to determine whether timing of a slope section of waveform of an analog signal ANS of a measurement target device is within a range of specifications. An ADC performs AD-conversion only when a potential of analog signal ANS is within a range between reference potentials VOL, VOH. An analysis unit analyzes digital data from the ADC, and conducts a sloping waveform test to evaluate a sloping state of the waveform of analog signal ANS. Therefore, the slope section of the waveform of analog signal ANS of the device can be subjected to AD-conversion in a voltage range divided in arbitrary number of sections within a range of arbitrary voltage amplitude without requiring a large-capacity storage circuit. The function test by a determination circuit and the sloping waveform test by the analysis unit can be performed in parallel.
摘要:
A system for measuring and storing the amplitudes plus duration and/or rise times of overvoltage pulses occurring on a transmission line comprises a voltage divider working into a first and a second comparator respectively detecting an abnormal voltage exceeding a predetermined sensitivity threshold and discriminating among different amplitude levels above that threshold. The first comparator triggers an oscillator driving a pulse counter which measures the duration of an overvoltage pulse and also provides quantized information on rise time to the highest amplitude threshold surpassed by that pulse as determined by the second comparator. This information is stored in a memory with two groups of cells respectively assigned to combinations of amplitude with duration and combinations of amplitude with rise time, the occurrence of any such combination incrementing the contents of the respective cell. These cells are cyclically scannable and their contents can be selectively displayed on a visualizer such as an oscilloscope.
摘要:
A circuit and a method for measuring rising or falling time of high-speed data are disclosed. The circuit includes a comparator and a storage circuit. The comparator receives the high-speed data via a first port and a reference signal via a second port, compares a level of the high-speed data with a level of the reference signal in response to an enable signal, and outputs the compared result as a signal. A reference signal generator generates the reference signal. An enable signal generator generates the enable signal. The storage circuit receives and stores the signal and measures the rising or falling time of the high-speed data.
摘要:
An apparatus to be employed within a precision distance measuring system for estimating pulse time-of-arrival. The apparatus facilitates the use of an Adaptive Fixed Threshold method for such estimation. The invention compensates for pulse time detection errors induced by variations in incident pulse amplitude and shape by adjusting the estimated time-of-arrival. This adjustment is performed as a function of the measured pulse slope between two low-amplitude threshold levels through the use of a predetermined reference table of error adjustment times.
摘要:
A timing generator for generating timing signals representing the leading and trailing edges of test pulses. In one embodiment of the invention, a period circuit repetitively measures time intervals, or periods, based on signals from a clock circuit, and a marker circuit generates timing signals representing leading edge and trailing edge markers precisely within each period. The period circuit comprises a period-end memory having a plurality of storage locations which are addressed by a modulo(n) counter. To support multiple timing sets, or timing cycles, one or more of the most significant bits of the address field for the period-end memory may be reserved for designating each timing signal. The time interval measured by the period-end memory may be selectively extended by delaying the clocking signal used for incrementing the modulo(n) counter. The marker circuit comprises leading edge and trailing edge marker memories for storing values indicating where in a period a leading edge or a trailing edge marker is generated. The marker circuit further comprises extended cycle leading edge and trailing edge marker memories for storing values indicating where in a later timing cycle a marker is to be generated. Leading edge and trailing edge marker vernier memories are provided for storing values used to indicate the exact placement of markers within the time interval. Leading edge and trailing edge end-of-cycle marker memories are used for generating leading edge and trailing edge markers at the end of a particular timing cycle. Leading edge and trailing edge marker inhibit memories are used for inhibiting marker generation within a particular timing cycle.