公开(公告)号：US20220128614A1

公开(公告)日：2022-04-28

申请号：US17600151

申请日：2020-04-23

Applicant: HITACHI, LTD.

Inventor： Hiromichi YAMADA ,  Tatsuya MARUYAMA ,  Mitsuyasu KIDO

IPC: G01R31/12

Abstract: A distribution pattern of a combination of a charge quantity and an occurrence phase angle of each of the partial discharges occurring in one or a plurality of cycle periods of an applied voltage of the power transmission cable is generated, differential data including a difference between the numbers of occurrences of the partial discharge for each combination of the charge quantity and the occurrence phase angle in two or more latest distribution patterns is generated, and the degree of progress of the partial discharge is determined based on data of the latest distribution patterns and the differential data.

公开(公告)号：US20210231747A1

公开(公告)日：2021-07-29

申请号：US17098771

申请日：2020-11-16

Applicant: Hitachi, Ltd.

Inventor： Hiromichi YAMADA ,  Mitsuyasu KIDO

IPC: G01R31/52 ,  G01R31/58 ,  G06N3/08

Abstract: An object of the present invention is to propose a partial discharge determination device and method that can highly reliably determine the degree of progress of partial discharge occurring in an underground power transmission cable without preparing plural standard patterns. A distribution pattern of a set of the charge amount and the occurrence phase angle of each partial discharge occurring in a period of one or more cycles of an applied voltage of a power transmission cable is sequentially generated, a first classification process in which the pattern is classified into any one of classes on the basis of a standard distribution pattern for each class and a second classification process in which the distribution pattern are executed, a classification result by the first classification process is evaluated on the basis of a classification result by the second classification process, and the degree of progress is determined.

公开(公告)号：US20180165153A1

公开(公告)日：2018-06-14

申请号：US15317230

申请日：2014-06-18

Applicant: Hitachi, Ltd.

Inventor： Hiromichi YAMADA ,  Tsutomu YAMADA

IPC: G06F11/10 ,  G11C29/52 ,  G11C11/4076 ,  G11C11/409

CPC classification number: G06F11/1068 ,  G06F11/1048 ,  G06F11/18 ,  G06F12/16 ,  G11C11/4076 ,  G11C11/409 ,  G11C29/52 ,  G11C29/702 ,  G11C29/74 ,  G11C2029/0409 ,  G11C2029/0411

Abstract: Provided is an integrated circuit or the like capable of rapidly correcting erroneous data write and making contents of the RAMs that are in the multiple modular redundancy coincident in a case where a logic circuit performs the erroneous data write to the RAMs while operating logic circuits and RAMs at a high speed. In order to solve the problem, the integrated circuit including logic circuits and RAMs for which data write and data read are performed by the logic circuits includes a multiple modular redundancy logic circuits, a plurality of RAMs respectively connected to the multiple modular redundancy logic circuits, and a RAM access correction unit which compares access signals from the multiple modular redundancy logic circuit to the RAMs to detect an erroneous data write and corrects an error of the RAM.

公开(公告)号：US20240183894A1

公开(公告)日：2024-06-06

申请号：US18284934

申请日：2022-06-07

Applicant: HITACHI, LTD.

Inventor： Hiromichi YAMADA ,  Shinsuke ONOE ,  Mitsuyasu KIDO

IPC: G01R31/14 ,  G01R31/28 ,  G01R31/58

CPC classification number: G01R31/14 ,  G01R31/2846 ,  G01R31/58

Abstract: A partial discharge determination method executed in a partial discharge determination apparatus that determines whether or not partial discharge has occurred in a power transmission facility includes: acquiring measurement data representing a charge amount and a phase of each partial discharge occurring in the power transmission facility; removing or reducing noise included in the measurement data based on statistical information; generating φ-q-n data representing a charge amount, a phase, and the number of pulses of each of the partial discharge and the noise included in the measurement data from the measurement data from which the noise has been removed or reduced; and determining whether or not at least the partial discharge has occurred by using a learning model generated by performing machine learning using the φ-q-n data of the partial discharge and the noise based on the φ-q-n data generated by a φ-q-n data generation unit.

公开(公告)号：US20240310425A1

公开(公告)日：2024-09-19

申请号：US18281822

申请日：2022-03-23

Applicant: HITACHI, LTD.

Inventor： I KYU ,  Shigeki KATAYAMA ,  Hiromichi YAMADA

IPC: G01R31/12 ,  G01R31/14

CPC classification number: G01R31/1272 ,  G01R31/14

Abstract: Provided is an insulation degradation diagnosis apparatus that performs an insulation degradation diagnosis based on a partial discharge signal of an insulator, the device including: a characteristic diagram creation unit configured to create a φ-q-n characteristic diagram of a partial discharge signal of an insulator to be determined; an image creation unit configured to create a φ-q-n image having each pixel value based on each numerical value of a φ-q-n characteristic diagram; and a diagnosis unit configured to make a diagnosis on a presence or occurrence state of partial discharge in the insulator to be determined, using an insulation degradation diagnosis model which is created by learning a φ-q-n image having each pixel value based on each numerical value of a φ-q-n characteristic diagram of a partial discharge signal of an insulator for learning as training data associated with a presence or occurrence state of partial discharge.

公开(公告)号：US20170094375A1

公开(公告)日：2017-03-30

申请号：US15182692

申请日：2016-06-15

Applicant: Hitachi, Ltd.

Inventor： Hiromichi YAMADA ,  Tsutomu YAMADA ,  Tatsuya MARUYAMA

IPC: H04Q3/56 ,  H04L12/815 ,  H04L12/741 ,  H04L29/06 ,  H04L12/931

CPC classification number: H04Q3/56 ,  H04L45/745 ,  H04L47/23 ,  H04L49/351 ,  H04L69/22 ,  H04Q2213/13322

Abstract: Provided are a communication processing device and a communication system, capable of securely updating a communication protocol process with a simple configuration and technique, while continuing communication. A communication processing device, which is connected to a communication network, includes a programmable logic device in which partial rewriting of a logic circuit is possible, during an operation of a host device in the communication network, in which the programmable logic device includes at least two communication processing circuits of which each performs a communication protocol process, and in which one communication processing circuit is operable due to switching, a first communication processing circuit performs communication, and a second communication processing circuit is on standby, updating means for downloading logic circuit data of an updated communication protocol process, from the communication network, and performing a circuit configuration for the second communication processing circuit, a flag that indicates whether or not the circuit configuration for the second communication processing circuit is finished, and by which a circuit configuration state is able to be read to the host device side through communication, and a register that is intended for switching to any one communication processing circuit to be used, and is writable from the host device side through communication.

公开(公告)号：US20160335145A1

公开(公告)日：2016-11-17

申请号：US15110278

申请日：2014-01-24

Applicant: Hitachi, Ltd.

Inventor： Tadanobu TOBA ,  Kenichi SHIMBO ,  Yusuke KANNO ,  Nobuyasu KANEKAWA ,  Kotara SHIMAMURA ,  Hiromichi YAMADA

IPC: G06F11/07 ,  H03K19/177

CPC classification number: G06F11/079 ,  G06F11/0727 ,  G06F11/073 ,  G06F11/0751 ,  G06F11/0754 ,  G06F11/0772 ,  G06F11/0793 ,  H03K19/1776 ,  H03K19/17764

Abstract: The present invention aims to provide a programmable device with a configuration memory that can hold the state of the occurrence abnormal situation that is difficult to assume such as a failure occurring in the programmable device due to the terrestrial radiation of the configuration memory, even during power off, in order to improve the reproducibility in device testing based on the held error information. The programmable device with the configuration memory includes: an error detection section for detecting an error in the configuration memory, and outputting the detected error as well as an address in which the error occurred, as error information; and an error information holding section provided with a non-volatile memory to store the output error information.

Abstract translation: 本发明的目的在于提供一种具有配置存储器的可编程设备，即使在电源期间，由于配置存储器的地面辐射，可以保持难以产生的发生异常情况的状态，例如在可编程设备中发生的故障 以提高基于所保持的错误信息的设备测试中的再现性。 具有配置存储器的可编程设备包括：错误检测部分，用于检测配置存储器中的错误，并将检测到的错误以及发生错误的地址输出作为错误信息; 以及设置有用于存储输出错误信息的非易失性存储器的错误信息保持部。