公开(公告)号：US20170322845A1

公开(公告)日：2017-11-09

申请号：US15531795

申请日：2015-06-01

Applicant: Hitachi, Ltd.

Inventor： Shimpei NOMURA ,  Akifumi SUZUKI ,  Mitsuhiro OKADA ,  Satoshi MORISHITA

IPC: G06F11/10 ,  G06F3/06

CPC classification number: G06F11/1076 ,  G06F3/0613 ,  G06F3/0659 ,  G06F3/0689 ,  G06F12/0804

Abstract: A purpose is to speed up a write process with a parity update. An information processing system includes storage devices constituting a RAID group, coupled to one bus and communicating with each other. Each of the storage devices includes a device controller and a storage medium for storing data. The storage devices include a first storage device storing old data and a second storage device storing old parity associated with the old data. A first device controller of the first storage device creates intermediate parity based on the old data and new data for updating the old data and transmit the intermediate parity to the second storage device specifying the second storage device storing the old parity associated with the old data, and a second device controller of the second storage device creates new parity based on the intermediate parity and the old parity.

公开(公告)号：US20180011812A1

公开(公告)日：2018-01-11

申请号：US15545461

申请日：2015-02-25

Applicant: Hitachi, Ltd.

Inventor： Satoshi MORISHITA ,  Mitsuhiro OKADA ,  Akifumi SUZUKI ,  Shimpei NOMURA

IPC: G06F13/42 ,  G06F12/02

CPC classification number: G06F13/4221 ,  G06F3/0613 ,  G06F3/0635 ,  G06F3/0658 ,  G06F3/067 ,  G06F12/0215 ,  G06F13/00 ,  G06F13/10 ,  G06F13/12 ,  G06F13/126 ,  G06F13/14 ,  G06F13/4022 ,  G06F2213/0026

Abstract: An information processing device having a processor and memory, and including one or more accelerators and one or more storage devices, wherein: the information processing device has one network for connecting the processor, the accelerators, and the storage devices; the storage devices have an initialization interface for accepting an initialization instruction from the processor, and an I/O issuance interface for issuing an I/O command; and the processor notifies the accelerators of the address of the initialization interface or the address of the I/O issuance interface.

公开(公告)号：US20180018231A1

公开(公告)日：2018-01-18

申请号：US15548635

申请日：2015-02-25

Applicant: HITACHI, LTD.

Inventor： Mitsuhiro OKADA ,  Akifumi SUZUKI ,  Satoshi MORISHITA ,  Akira YAMAMOTO

IPC: G06F11/10 ,  G06F3/06

Abstract: A storage unit includes a plurality of storage devices that form a RAID group, that are coupled to the same bus, and that communicate with each other. Each of the plurality of storage devices includes a device controller and a storage medium. The plurality of storage devices store each of data and parities generated on the basis of the data, the data and the parities being included in RAID stripes. A first device controller of a first storage device included in the RAID group transmits, to the plurality of storage devices included in the RAID group other than the first storage device, an instruction to transfer the data and/or the parities included in the RAID stripes and restores the data or the parity corresponding to the first storage device of the RAID stripes on the basis of the transferred data and the transferred parities.

公开(公告)号：US20170308319A1

公开(公告)日：2017-10-26

申请号：US15518289

申请日：2014-11-04

Applicant: Hitachi, Ltd.

Inventor： Akifumi SUZUKI ,  Mitsuhiro OKADA ,  Satoshi MORISHITA

IPC: G06F3/06

CPC classification number: G06F3/0635 ,  G06F3/0611 ,  G06F3/0656 ,  G06F3/0659 ,  G06F3/0679 ,  G06F12/00 ,  G06F12/06 ,  G06F12/08 ,  G06F12/16

Abstract: The semiconductor memory device comprises a memory element group (one or more semiconductor memory elements) and a memory controller. The memory controller comprises a processor configured to process at least a part of an I/O command from a higher-level apparatus when the part of the I/O command satisfies a predetermined condition, and one or more hardware logic circuits configured to process the entire I/O command when the I/O command does not satisfy the predetermined condition.

公开(公告)号：US20160342545A1

公开(公告)日：2016-11-24

申请号：US15114573

申请日：2014-02-12

Applicant: HITACHI, LTD.

Inventor： Masahiro ARAI ,  Akifumi SUZUKI ,  Mitsuhiro OKADA ,  Yuji ITO ,  Kazuei HIRONAKA ,  Satoshi MORISHITA ,  Norio SHIMOZONO

IPC: G06F13/28 ,  G06F11/07 ,  G06F13/16 ,  G06F13/42 ,  G06F3/06 ,  G06F12/0868

CPC classification number: G06F13/28 ,  G06F3/061 ,  G06F3/0638 ,  G06F3/0656 ,  G06F3/0659 ,  G06F3/0683 ,  G06F3/0689 ,  G06F11/0727 ,  G06F11/0751 ,  G06F11/0772 ,  G06F12/0868 ,  G06F13/1673 ,  G06F13/4282 ,  G06F2212/1016 ,  G06F2212/401 ,  G06F2213/0026

Abstract: A data memory device has a command transfer direct memory access (DMA) engine configured to obtain a command that is generated by an external apparatus to give a data transfer instruction from a memory of the external apparatus; obtain specifics of the instruction; store the command in a command buffer; obtain a command number that identifies the command being processed; and activate a transfer list generating DMA engine by transmitting the command number depending on the specifics of the instruction of the command. The transfer list generating DMA engine is configured to: identify, based on the command stored in the command buffer, an address in the memory to be transferred between the external apparatus and the data memory device; and activate the data transfer DMA engine by transmitting the address to the data transfer DMA engine which then transfers the data to/from the memory based on the received address.

Abstract translation: 数据存储装置具有命令传送直接存储器存取（DMA）引擎，其被配置为获得由外部装置生成的命令，以从外部装置的存储器提供数据传送指令; 获取该指令的细节; 将命令存储在命令缓冲区中; 获取标识正在处理的命令的命令编号; 并且通过根据该命令的指令的细节发送命令号码来激活生成DMA引擎的传送列表。 传输列表生成DMA引擎被配置为：基于存储在命令缓冲器中的命令，识别要在外部设备和数据存储设备之间传送的存储器中的地址; 并通过将地址发送到数据传输DMA引擎来激活数据传输DMA引擎，该数据传输DMA引擎基于接收的地址将数据传送到/从存储器传送数据。