公开(公告)号：US20240427624A1

公开(公告)日：2024-12-26

申请号：US18603265

申请日：2024-03-13

Applicant: Hitachi, Ltd.

Inventor： Yoshihiro YOSHII ,  Tomohiro YOSHIHARA ,  Takashi NAGAO ,  Ryosuke TATSUMI

IPC: G06F9/455 ,  G06F12/02

Abstract: The present invention achieves high throughput by making efficient use of virtual device resources. A storage system includes a storage device and a processor. The processor manages a primary volume and a snapshot volume as a snapshot family. The processor uses a snapshot virtual device as the data storage destination for the primary volume and for the snapshot volume. Upon receiving a write request from a host, the processor switches between an overwrite process and a new allocation process in accordance with the reference made to a write destination address range by the snapshot volume and with the degree of distribution of the write destination address range in the snapshot virtual device. The overwrite process is performed to overwrite an allocated area of the snapshot virtual device. The new allocation process is performed to allocate a new area of the snapshot virtual device to the write destination address range.

公开(公告)号：US20230297242A1

公开(公告)日：2023-09-21

申请号：US17947905

申请日：2022-09-19

Applicant: Hitachi, Ltd.

Inventor： Kenichi BETSUNO ,  Akira YAMAMOTO ,  Takashi NAGAO ,  Kazuki MATSUGAMI

IPC: G06F3/06 ,  G06F11/10

CPC classification number: G06F3/0616 ,  G06F11/10 ,  G06F3/0631 ,  G06F3/0683 ,  G06F12/0253

Abstract: A storage device manages data stored in a storage drive in a plurality of logical hierarchies. The plurality of logical hierarchies include a writing hierarchy above a hierarchy of a parity group including a plurality of storage drives. The storage device writes received host data in a free area in the writing hierarchy. In the data recovery process for replacing a failure storage drive with a new storage drive, the storage device executes the garbage collection process on a first logical area in the writing hierarchy associated with the first parity group including the failure storage drive. In the garbage collection process, valid data is selected from the first logical area and copied to a second logical area associated with a second parity group different from the first parity group.

公开(公告)号：US20210165753A1

公开(公告)日：2021-06-03

申请号：US17169775

申请日：2021-02-08

Applicant: Hitachi, Ltd.

Inventor： Yuto KAMO ,  Ryosuke TATSUMI ,  Tomohiro YOSHIHARA ,  Takashi NAGAO

IPC: G06F13/28 ,  G06F12/0868

Abstract: An object of the present invention is to properly secure the consistency of data while suppressing a processing load of a controller on a processor. A storage system includes a plurality of controllers and an HCA that can directly access a memory and can communicate with the controllers. The controller includes a CPU, and a memory having a buffer region into which data is temporarily stored and a cache region into which data is cached. In the case where new data according to a write request is stored into the buffer region, the CPU of the controller sequentially transfers the new data to the cache regions using the HCA without passing through the other buffer regions.

公开(公告)号：US20170060478A1

公开(公告)日：2017-03-02

申请号：US15119860

申请日：2014-09-11

Applicant: HITACHI, LTD.

Inventor： Takashi NAGAO ,  Tomohiro KAWAGUCHI ,  Yoshinori OOHIRA

IPC: G06F3/06

CPC classification number: G06F3/0659 ,  G06F3/06 ,  G06F3/0604 ,  G06F3/0619 ,  G06F3/0656 ,  G06F3/067 ,  G06F11/008 ,  G06F11/2069 ,  G06F11/2082 ,  G06F11/3051

Abstract: A processor receives a command from a server computer to designate a plurality of addresses related to a plurality of logical storage areas, and write a plurality of write data to the logical storage areas. The processor receives the write data and writes it to storage areas different from storage areas in which a plurality of holding data are stored in a first memory. When the processor determines that the write data are written to the first memory, the processor transmits a success response to a host computer. When the write data satisfy a predetermined condition, the processor writes the write data in the first memory to a plurality of first device storage areas. When it is determined that at least a part of the data is not written to the first memory, the processor transmits a failure response to the host computer.

Abstract translation: 处理器从服务器计算机接收指定与多个逻辑存储区域相关的多个地址的命令，并将多个写入数据写入逻辑存储区域。 处理器接收写入数据，并将其写入与多个保持数据存储在第一存储器中的存储区域不同的存储区域。 当处理器确定写入数据被写入到第一存储器时，处理器向主计算机发送成功响应。 当写数据满足预定条件时，处理器将第一存储器中的写入数据写入多个第一设备存储区域。 当确定至少一部分数据未被写入第一存储器时，处理器向主计算机发送故障响应。

公开(公告)号：US20150370484A1

公开(公告)日：2015-12-24

申请号：US14765275

申请日：2013-08-20

Applicant: HITACHI, LTD.

Inventor： Tomohiro KAWAGUCHI ,  Akira YAMAMOTO ,  Shigeo HOMMA ,  Takashi NAGAO

IPC: G06F3/06

CPC classification number: G06F3/0604 ,  G06F3/0611 ,  G06F3/0647 ,  G06F3/0659 ,  G06F3/0683 ,  G06F3/0689

Abstract: Proposed are a storage apparatus and a data input/output method capable of improving the response performance of the overall storage apparatus. When a storage controller of a storage apparatus receives a first read command that designates a plurality of storage areas in the logical volume as a read destination, the storage controller identifies the storage media and address that are actually storing the data written into the storage area, creates, for each of the storage media, a second read command that designates a part or all of each of the identified addresses in the identified storage media as a read destination and sends each of the created second read commands to the corresponding storage media, and transfers, to the host computer, the data that was read from each of the addresses designated in the second read command and sent from each of the storage media that sent the second read command.

Abstract translation: 提出了能够提高整体存储装置的响应性能的存储装置和数据输入/输出方法。 当存储装置的存储控制器接收到将逻辑卷中的多个存储区域指定为读取目的地的第一读取命令时，存储控制器识别实际存储写入存储区域的数据的存储介质和地址， 为每个存储介质创建第二读取命令，其将所识别的存储介质中的每个所识别的地址的一部分或全部指定为读取目的地，并将所创建的第二读取命令中的每一个发送到相应的存储介质，以及 将从第二读取命令中指定的每个地址读取的数据传送到主计算机，并从发送第二读取命令的每个存储介质发送。

公开(公告)号：US20250044968A1

公开(公告)日：2025-02-06

申请号：US18602472

申请日：2024-03-12

Applicant: Hitachi, Ltd.

Inventor： Takashi NAGAO ,  Tomohiro YOSHIHARA ,  Jun MIYASHITA ,  Masahiro TSURUYA

IPC: G06F3/06

Abstract: A storage device includes a processor and an accelerator configured to compress and decompress data. The processor receives first replacement write data for a part of a first logical address region to update first data in the first logical address region that has been compressed by basic compression unit. The processor instructs the accelerator to compress the first replacement write data by a size smaller than the basic compression unit. The accelerator compresses the first replacement write data by the smaller size. The processor merges not-to-be-replaced data in the first logical address region and the first replacement data that are decompressed by the accelerator to generate uncompressed data having a size of the basic compression unit. The processor instructs the accelerator to compress the uncompressed data by the basic compression unit.

公开(公告)号：US20230280945A1

公开(公告)日：2023-09-07

申请号：US17942310

申请日：2022-09-12

Applicant: Hitachi, Ltd.

Inventor： Ryosuke TATSUMI ,  Takashi NAGAO ,  Kazuki MATSUGAMI

IPC: G06F3/06

CPC classification number: G06F3/0679 ,  G06F3/0619 ,  G06F3/0655

Abstract: A storage system holds upper mapping information and lower mapping information. The upper mapping information manages an address relationship between a logical device upper layer accessed by a host and a logical device middle layer. The lower mapping information manages an address relationship between the logical device middle layer and a logical device lower layer. The lower mapping information includes pieces of partial mapping information. Each of the pieces of partial mapping information manages address information of a partial area in the logical device middle layer. The storage system writes, in response to a failure of first partial mapping information in the lower mapping information, new data that fills a first partial area in the logical device middle layer managed by the first partial mapping information, and regenerates the first partial mapping information.

公开(公告)号：US20220121402A1

公开(公告)日：2022-04-21

申请号：US17561814

申请日：2021-12-24

Applicant: Hitachi, Ltd.

Inventor： Takashi NAGAO ,  Tomohiro YOSHIHARA ,  Akira YAMAMOTO ,  Yuusaku KIYOTA

IPC: G06F3/06 ,  H03M7/30

Abstract: The present invention realizes a storage device that has a high data reduction effect without decreasing I/O performances. The storage device includes a processor, an accelerator, a memory, and a storage medium, the processor specifies data to be compressed that is data stored in the storage medium from data stored in the memory and transmits a compression instruction including information relating to the data to be compressed to the accelerator, and the accelerator reads the plurality of continuous items of data from the memory and compresses the plurality of items of data to be compressed obtained by excluding data that is not to be compressed from the plurality of items of data, based on the information relating to the data to be compressed received from the processor, to generate compressed data stored in the storage device.

公开(公告)号：US20200310975A1

公开(公告)日：2020-10-01

申请号：US16568314

申请日：2019-09-12

Applicant: Hitachi, Ltd.

Inventor： Naoya OKADA ,  Tomohiro YOSHIHARA ,  Takashi NAGAO ,  Ryosuke TATSUMI

IPC: G06F12/0871 ,  G06F12/14 ,  G06F3/06

Abstract: A storage system includes a plurality of controllers and a plurality of storage drives. A first cache area and a second cache area are set in a memory. The first cache area is permitted to be written data by the plurality of storage drives, and the second cache area is not permitted to be written data by the plurality of storage drives. In a case where the plurality of controllers duplicates data stored in the cache area to a cache area of another controller for redundancy, the plurality of controllers causes the data to be redundant in a second cache area of the other controller in a case where the data is stored in the first cache area, and causes the data to be redundant in a first cache area of the other controller in a case where the data is stored in the second cache area.

公开(公告)号：US20170300233A1

公开(公告)日：2017-10-19

申请号：US15509597

申请日：2014-10-28

Applicant: Hitachi, Ltd.

Inventor： Takamasa SATO ,  Takashi SAKAGUCHI ,  Azusa JIN ,  Kensuke NARITA ,  Yosuke KATOH ,  Takashi NAGAO

IPC: G06F3/06

CPC classification number: G06F3/065 ,  G06F3/0617 ,  G06F3/0683 ,  G06F11/1456 ,  G06F11/1458 ,  G06F11/1658

Abstract: A storage system forms a high availability pair for data duplication using a first volume of a first storage apparatus as a primary volume and a second volume of a second storage apparatus as a secondary volume. The first volume and a third volume of a third storage apparatus are used as a primary volume and a secondary volume, respectively, to form an asynchronous copy pair. The second volume and the third volume are used as a primary volume and a secondary volume, respectively, to form a standby pair. When a command to form the asynchronous copy pair is received, the storage system refuses to form the asynchronous copy pair when the standby pair is not formed yet.