公开(公告)号：US20230384952A1

公开(公告)日：2023-11-30

申请号：US18138793

申请日：2023-04-25

Applicant: Hitachi, Ltd.

Inventor： Shumpei MORITA ,  Tomoyuki KAMAZUKA ,  Hideaki MONJI ,  Yuusaku KIYOTA

IPC: G06F3/06 ,  G06F21/60

CPC classification number: G06F3/0622 ,  G06F3/0683 ,  G06F3/0631 ,  G06F21/602

Abstract: A storage system that can achieve a cryptographic operation circuit that supports multiple types of cryptographic operation formats. The cryptographic operation circuit is provided that encrypts data according to the format determined by the processor based on a request by the host terminal for writing the data into the storage device, and decrypts the encrypted data on the data stored in the storage device according to the format determined by the processor based on a request by the host terminal for reading the data from the storage device.

公开(公告)号：US20210264063A1

公开(公告)日：2021-08-26

申请号：US17029340

申请日：2020-09-23

Applicant: Hitachi, Ltd.

Inventor： Hideaki MONJI ,  Yuusaku KIYOTA

IPC: G06F21/78 ,  G06F21/60 ,  G06F12/14 ,  G06F11/10

Abstract: Encryption is enabled at a low load in a storage system. An encryption processing device 20 uses, as an expectation value for key validation, a value that is uniquely identified from a storage location address of encrypted text data in a storage drive. The encryption processing device 20 encrypts the expectation value and plain text data, respectively, using a same encryption key, substitutes a DIF according to the encrypted text data obtained by encrypting the plain text data, and stores the encrypted expectation value in the substituted DIF. Upon receiving a read request of the encrypted text data, the encryption processing device 20 decrypts the encrypted expectation value stored in the substituted DIF using a decryption key, and validates whether the encryption key and the decryption key are properly corresponding by comparing the decrypted expectation value and the expectation value identified from the address at the time of reading.

公开(公告)号：US20240184460A1

公开(公告)日：2024-06-06

申请号：US18119790

申请日：2023-03-09

Applicant: Hitachi, Ltd.

Inventor： Tomoyuki KAMAZUKA ,  Yuusaku KIYOTA

IPC: G06F3/06

CPC classification number: G06F3/0626 ,  G06F3/0629 ,  G06F3/0673

Abstract: A compression-expansion control apparatus has a reconfiguration portion capable of configuring one or more compression circuits which compress data in plain text and/or one or more expansion circuits which expand the compressed data on a programmable logical circuit component, a waiting-time observing portion which observes processing waiting-time from when compression processing was requested till when the compression processing is started and processing waiting-time from when expansion processing was requested till when the expansion processing is started, a calculating portion which determines the number or a ratio of the compression circuits and the expansion circuits in the reconfiguration portion on the basis of the processing waiting-time of the compression processing and the processing waiting-time of the expansion processing, and a switching portion which executes reconfiguration of the compression circuit and/or the expansion circuit in the reconfiguration portion on the basis of the number or the ratio determined by the calculating portion.

公开(公告)号：US20240088919A1

公开(公告)日：2024-03-14

申请号：US18125188

申请日：2023-03-23

Applicant: Hitachi, Ltd.

Inventor： Tomoyuki KAMAZUKA ,  Kenshiro HIMOTO ,  Shoji KATO ,  Yuusaku KIYOTA

IPC: H03M13/00 ,  H03M7/30

CPC classification number: H03M13/6312 ,  H03M7/6041

Abstract: In a compression mode in which plaintext data is input, and compressed, a first code that is an error detection code is generated with respect to the plaintext data, and compressed. A circuit generates restored plaintext data in which the compressed data is decompressed, for confirming successfulness. A second code that is an error detection code is generated with respect to the restored plaintext data and is compared with the first code. In a case where the first code and the second code agree, the compressed data and the first or second code are output. In a decompression mode, plaintext data is generated in which the input compressed data is decompressed. A third code that is an error detection code is generated with respect to the plaintext data and is compared with an input code, and when the input code and the third code agree, the plaintext data is output.

公开(公告)号：US20250077339A1

公开(公告)日：2025-03-06

申请号：US18599302

申请日：2024-03-08

Applicant: Hitachi, Ltd.

Inventor： Tomoyuki KAMAZUKA ,  Ryota TATSUUMA ,  Shoji KATO ,  Yuusaku KIYOTA

IPC: G06F11/07

Abstract: A data processing system includes: a processor implemented by a programmable device; and a processor processing unit connected to the processor. The processor includes a plurality of processing circuits configured to execute in parallel data processing commands provided from the processor processing unit, an error detection unit configured to detect a soft error occurring in a processing circuit that is executing the data processing command, and a processing circuit selection unit configured to select a processing circuit to execute the data processing command from a plurality of processing circuits. The processing circuit selection unit specifies a processing circuit in which the soft error occurs based on a soft error detection result of the error detection unit, and selects a processing circuit to execute the data processing command from the plurality of processing circuits, excluding the processing circuit in which the soft error occurs.

公开(公告)号：US20220308761A1

公开(公告)日：2022-09-29

申请号：US17692255

申请日：2022-03-11

Applicant: Hitachi, Ltd.

Inventor： Kenichi BETSUNO ,  Takashi NAGAO ,  Yuusaku KIYOTA ,  Tomohiro YOSHIHARA

IPC: G06F3/06

Abstract: Provided is a storage system including a plurality of controllers. The storage system adopts a write-once data storage system and can implement high Input/Output (I/O) processing performance while ensuring data consistency when a failure occurs. Before metadata duplication, recovery data including information necessary for performing roll forward or roll back is stored in each controller, and then the metadata duplication is performed. A recovery data storage processing and the metadata duplication are offloaded to a hardware accelerator.

公开(公告)号：US20220229561A1

公开(公告)日：2022-07-21

申请号：US17716002

申请日：2022-04-08

Applicant: Hitachi, Ltd.

Inventor： Takashi NAGAO ,  Yuusaku KIYOTA ,  Hideaki MONJI ,  Tomohiro YOSHIHARA

IPC: G06F3/06

Abstract: A storage system having high reliability and IO processing performance is realized. The storage system includes: a first arithmetic unit configured to receive an input and output request and perform data input and output processing; a first memory connected to the first arithmetic unit; a plurality of storage drives configured to store data; a second arithmetic unit; and a second memory connected to the second arithmetic unit. The first arithmetic unit instructs the storage drive to read data, the storage drive reads the data and stores the data in the second memory, the second arithmetic unit stores the data stored in the second memory in the first memory, and the first arithmetic unit transmits the data stored in the first memory to a request source of a read request for the data.

公开(公告)号：US20150363220A1

公开(公告)日：2015-12-17

申请号：US14763946

申请日：2013-02-01

Applicant: HITACHI, LTD.

Inventor： Yosuke YAMADA ,  Yuusaku KIYOTA ,  Tooru IBA

IPC: G06F9/455 ,  G06F3/06 ,  G06F13/16

CPC classification number: G06F9/45558 ,  G06F3/0613 ,  G06F3/0665 ,  G06F3/0689 ,  G06F9/50 ,  G06F13/1642 ,  G06F2009/45579

Abstract: A computer has an adapter which is coupled to storage devices; the adapter transmits data and receives data, and measures the transfer amount of data that has been transmitted and received, and the number of I/O accesses, for each virtual computer; a virtualization part, on the basis of the transfer amount of the data, and the number of I/O accesses, acquired from the adapter, computes an upper limit for the data transfer amount and an upper limit for the number of I/O accesses for each virtual computer and reports to the virtual computers; and the virtual computers retain the data to transfer to and to receive from the storage devices in a queue, and the virtual computers control data to output from the queue so as not to exceed the upper limit of the data transfer amount or the number of I/O accesses.

Abstract translation: 计算机具有耦合到存储设备的适配器; 适配器发送数据并接收数据，并测量已发送和接收的数据的传输量以及每个虚拟计算机的I / O访问次数; 基于数据传送量的虚拟化部分和从适配器获取的I / O访问的数量，计算数据传送量的上限和I / O访问次数的上限 为每个虚拟计算机报告虚拟电脑; 并且虚拟计算机保留数据以传送到队列中的存储设备并从其接收，并且虚拟计算机控制从队列输出的数据，以便不超过数据传送量或I的数量的上限 / O访问。

公开(公告)号：US20220131555A1

公开(公告)日：2022-04-28

申请号：US17192633

申请日：2021-03-04

Applicant: Hitachi, Ltd.

Inventor： Takeshi HIRAO ,  Yuusaku KIYOTA ,  Shoji KATO

IPC: H03M7/40 ,  H03M13/00

Abstract: A compression engine calculates replacement CRC codes, in predetermined data lengths, for DIF-in cleartext data including cleartext data and multiple CRC codes based on the cleartext data. The compression engine generates headered compressed-text data in which a header including the replacement CRC codes is added to compressed-text data in which the cleartext data is compressed, and generates code-in compressed-text data by calculating multiple CRC codes based on the headered compressed-text data to add the calculated CRC codes to the headered compressed-text data.

公开(公告)号：US20220121402A1

公开(公告)日：2022-04-21

申请号：US17561814

申请日：2021-12-24

Applicant: Hitachi, Ltd.

Inventor： Takashi NAGAO ,  Tomohiro YOSHIHARA ,  Akira YAMAMOTO ,  Yuusaku KIYOTA

IPC: G06F3/06 ,  H03M7/30

Abstract: The present invention realizes a storage device that has a high data reduction effect without decreasing I/O performances. The storage device includes a processor, an accelerator, a memory, and a storage medium, the processor specifies data to be compressed that is data stored in the storage medium from data stored in the memory and transmits a compression instruction including information relating to the data to be compressed to the accelerator, and the accelerator reads the plurality of continuous items of data from the memory and compresses the plurality of items of data to be compressed obtained by excluding data that is not to be compressed from the plurality of items of data, based on the information relating to the data to be compressed received from the processor, to generate compressed data stored in the storage device.