-
公开(公告)号：US20130335887A1
公开(公告)日：2013-12-19
申请号：US13915978
申请日：2013-06-12
Applicant: Hitachi, Ltd.
Inventor： Ayumu MORITA , Naoya OKADA , Akitaka SHIINA , Kenji TSUCHIYA , Mitsuaki YAMAMOTO , Hiroaki MORII , Takao YANAGISAWA
Abstract: A resistor for suppressing magnetizing inrush current includes a container made of an insulating material and at least one resistive element housed in the container, the resistive element being connected to two bushings provided at the container, the outer surface of the container being coated with a conductive paint, and the paint being connected to the ground, thereby being able to be located between a cable and a switch, and being able to fix the outer surface thereof to a ground voltage level so that human contact safety is not impaired.
Abstract translation: 用于抑制磁化冲击电流的电阻包括由绝缘材料制成的容器和容纳在容器中的至少一个电阻元件，电阻元件连接到设置在容器上的两个衬套，容器的外表面涂有导电 油漆和油漆连接到地面，从而能够位于电缆和开关之间，并且能够将其外表面固定到接地电压水平，使得人的接触安全性不受损害。
-
公开(公告)号：US20220337532A1
公开(公告)日：2022-10-20
申请号：US17462425
申请日：2021-08-31
Applicant: Hitachi, Ltd.
Inventor： Katsuya TANAKA , Naoya OKADA
IPC: H04L12/937 , H04L12/861 , H04L12/931
Abstract: A storage apparatus includes: a plurality of storage controllers including controller interfaces including a plurality of interface ports for connection to the plurality of switches having switch ports, a plurality of virtual networks configured by one of the switch ports is configured in the switch, and the storage controller sends a first packet for specifying the switch port to which the interface port is to be connected from the interface port to the plurality of virtual networks, and determines an address of the interface port used for data transfer between the storage controllers based on a switch number of the switch and a switch port number of the switch port in a case where a second packet including information for specifying the switch number of the switch and the switch port number of the switch port to which the interface port is to be connected is received.
-
公开(公告)号：US20200310975A1
公开(公告)日：2020-10-01
申请号：US16568314
申请日：2019-09-12
Applicant: Hitachi, Ltd.
Inventor： Naoya OKADA , Tomohiro YOSHIHARA , Takashi NAGAO , Ryosuke TATSUMI
IPC: G06F12/0871 , G06F12/14 , G06F3/06
Abstract: A storage system includes a plurality of controllers and a plurality of storage drives. A first cache area and a second cache area are set in a memory. The first cache area is permitted to be written data by the plurality of storage drives, and the second cache area is not permitted to be written data by the plurality of storage drives. In a case where the plurality of controllers duplicates data stored in the cache area to a cache area of another controller for redundancy, the plurality of controllers causes the data to be redundant in a second cache area of the other controller in a case where the data is stored in the first cache area, and causes the data to be redundant in a first cache area of the other controller in a case where the data is stored in the second cache area.
-
公开(公告)号：US20200159454A1
公开(公告)日：2020-05-21
申请号：US16552838
申请日：2019-08-27
Applicant: Hitachi, Ltd.
Inventor： Nobumitsu TAKAOKA , Tomohiro YOSHIHARA , Naoya OKADA
IPC: G06F3/06
Abstract: In a large-scale storage system configured by combining a plurality of storage modules, it is possible to improve a read performance for deduplicated data. A large-scale storage system includes a first storage module and a second storage module each connected to a computing machine, the first storage module and the second storage module being connected to each other by a network, the first controller determines whether second data that is same as first data requested to be written is already stored in the second storage module when the first storage module receives a write request from the computing machine, and the first controller determines whether to store the first data in the first storage medium or to refer to the second data in the second storage module in a case in which the second data is already stored in the second storage module.
-
公开(公告)号：US20230075635A1
公开(公告)日：2023-03-09
申请号：US17690965
申请日：2022-03-09
Applicant: Hitachi, Ltd.
Inventor： Kentaro SHIMADA , Takashi NAGAO , Naoya OKADA
IPC: G06F3/06
Abstract: A bandwidth between a second processor and a second memory is higher than a bandwidth between a first processor and a first memory. The first memory stores a read command from a host computer. The first processor analyzes a content of the read command, and in accordance with a result of the analysis, requests read data from the second processor. In response to the request from the first processor, the second processor reads the read data from one or more storage drives and stores the read data in the second memory. The second processor notifies the first processor that the read data is stored in the second memory. The first processor transfers the read data read from the second memory, to the host computer without storing the read data in the first memory.
-
Patent Agency Ranking
公开(公告)号：US20180052632A1
公开(公告)日：2018-02-22
申请号：US15552509
申请日：2015-05-11
Applicant: Hitachi, Ltd.
Inventor： Masanori TAKADA , Naoya OKADA , Mitsuo DATE , Tsutomu KOGA
CPC classification number: G06F3/0644 , G06F3/0607 , G06F3/064 , G06F3/0659 , G06F3/0661 , G06F3/067 , G06F3/0689 , G06F12/023 , G06F13/12 , G11C7/1078
Abstract: This storage system includes a processor, a memory, a storage drive, and an interface device. The storage drive determines a size of transfer data based on an offset value which is a value relating to a size between the beginning of a storage area in the memory for the transfer of the data to be transferred to the interface device and the beginning of the partition of the memory to which the beginning of the storage area belongs, and then transfers data to be transferred, which has the determined size, to the interface device. The interface device divides the transferred data into packets and transfers these packets to the processor. The processor then stores the packets transferred from the interface device in the memory on a unit of a partition.
-
公开(公告)号：US20210034482A1
公开(公告)日：2021-02-04
申请号：US16821562
申请日：2020-03-17
Applicant: Hitachi, Ltd.
Inventor： Yoshiaki DEGUCHI , Naoya OKADA , Ryosuke TATSUMI , Kentaro SHIMADA , Sadahiro SUGIMOTO
IPC: G06F11/20 , G06F11/07 , G06F11/30 , G06F9/4401 , G06F9/50 , G06F9/54 , G06F12/06 , G06F12/0873 , G06F1/24
Abstract: A storage system includes a first storage controller including a plurality of main storage media and one or more processor cores, and a second storage controller including a plurality of main storage media and one or more processor cores and performing communication with the first storage controller. Storage areas of the main storage media in the first storage controller are allocated to an address map. In response to the occurrence of failures in one or mode main storage media of the main storage media of the first storage controller, the first storage controller performs restarting to reallocate the storage areas of the main storage media excluding one or more main storage media having caused the failures to an address map reduced than before the occurrence of the failures. The second storage controller continues operating during the restarting of the first storage controller.
-
公开(公告)号：US20170277914A1
公开(公告)日：2017-09-28
申请号：US15506967
申请日：2014-11-12
Applicant: Hitachi, Ltd.
Inventor： Akihiko ARAKI , Yusuke NONAKA , Masanori TAKADA , Naoya OKADA
CPC classification number: G06F3/064 , G06F3/0634 , G06F3/0635 , G06F11/20 , G06F11/2007 , G06F11/2017
Abstract: When mounting hardware which is coupled to another portion by a plurality of paths with different applications, despite the hardware being a single device, and a failure occurs in any of the paths, there is a risk that the failure may propagate to other components unless the other paths are also blocked. In order to solve the problem described above, in a storage apparatus to which a device coupled by a plurality of coupling paths with different applications can be mounted, the present invention determines a block range at the time of an occurrence of a failure to be a device and a plurality of coupling paths coupled to the device, manages the block range, and upon an occurrence of a failure, executes failure handling which involves blocking an appropriate block range determined in advance by referring to the information.
-
公开(公告)号：US20160026537A1
公开(公告)日：2016-01-28
申请号：US14426790
申请日：2013-12-24
Applicant: HITACHI, LTD.
Inventor： Makio MIZUNO , Norio SHIMOZONO , Sadahiro SUGIMOTO , Naoya OKADA
CPC classification number: G06F11/1451 , G06F3/0619 , G06F3/064 , G06F3/065 , G06F3/0685 , G06F3/0689 , G06F11/14 , G06F12/0802 , G06F12/0866 , G06F2201/885 , G06F2212/1032
Abstract: A storage system 100 includes a storage apparatus 125 and a storage controller 115 configured to control the storage apparatus. The storage controller adds a predetermined flag 425 to every predetermined size of data requested by a host computer to be written to the storage system, and stores the resultant data in a cache memory 278C. Upon detecting a predetermined trigger for saving, the storage controller stores, in a nonvolatile memory 284, data with the flag added thereto out of the data stored in the cache memory. The storage controller detects, as unsaved data information 620, a data size and a storage location for data with no flag added thereto out of the data on the cache memory, and stores the detected unsaved data information in the nonvolatile memory in association with the data with the flag added thereto.
Abstract translation: 存储系统100包括被配置为控制存储装置的存储装置125和存储控制器115。 存储控制器将预定标志425添加到要由主计算机请求写入存储系统的每个预定大小的数据，并将结果数据存储在高速缓冲存储器278C中。 在检测到用于保存的预定触发器时，存储控制器在非易失性存储器284中将存储在高速缓存存储器中的数据中添加有标志的数据存储在存储器284中。 作为未保存的数据信息620，存储控制器将高速缓冲存储器中的数据中没有标记的数据的数据大小和存储位置检测出来，并将检测到的未保存的数据信息与数据相关联地存储在非易失性存储器中 加上标志。
-
公开(公告)号：US20240078347A1
公开(公告)日：2024-03-07
申请号：US18112079
申请日：2023-02-21
Applicant: Hitachi, Ltd.
Inventor： Nagamasa MIZUSHIMA , Yoshihiro YOSHII , Naoya OKADA
CPC classification number: G06F21/78 , G06F21/602 , G06F21/64
Abstract: A computer includes a processor including a plurality of registers, a memory, and a storage medium. A processor of a computer is configured to execute an encryption process of generating encrypted user data including a plurality of encrypted data blocks using the plurality of registers, and add a DIF including CRC to the encrypted data blocks and store the result in a storage medium. The encryption process includes repeatedly executing a first process of reading partial data from a predetermined number of the data blocks and storing the partial data in a first register, a second process of storing encrypted partial data obtained by encrypting the partial data stored in the first register in a second register, and a third process of executing an operation for calculating CRC using the encrypted partial data stored in the second register and storing a result of the operation in a third register.
-
-
-
-
-
-
-
-
-
Search Results
15
records
(took 0.014 seconds)
