公开(公告)号：US07382652B2

公开(公告)日：2008-06-03

申请号：US11564887

申请日：2006-11-30

Applicant: Hitoshi Shiga ,  Chih-Hung Wang ,  Chin Hsi Lin

Inventor： Hitoshi Shiga ,  Chih-Hung Wang ,  Chin Hsi Lin

IPC: G11C16/04

CPC classification number: G11C16/344 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/16 ,  G11C2211/5621

Abstract: A semiconductor memory device includes a memory cell array, data buffer, and column switch. The data buffer senses the potential of a bit line to determine data in a selected memory cell and hold readout data in a read. The data buffer detects both whether the whole data buffer holds “0” data and whether the whole data buffer holds “1” data. The column switch selects part of the data buffer and connects the part to a bus.

Abstract translation: 半导体存储器件包括存储单元阵列，数据缓冲器和列开关。 数据缓冲器检测位线的电位以确定所选择的存储单元中的数据并保持读取中的读出数据。 数据缓冲器检测整个数据缓冲器是否保持“0”数据以及整个数据缓冲器是否保持“1”数据。 列开关选择数据缓冲区的一部分，并将部件连接到总线。

公开(公告)号：US07161850B2

公开(公告)日：2007-01-09

申请号：US11292347

申请日：2005-12-02

Applicant: Hitoshi Shiga ,  Chih-Hung Wang ,  Chin Hsi Lin

Inventor： Hitoshi Shiga ,  Chih-Hung Wang ,  Chin Hsi Lin

IPC: G11C7/10

CPC classification number: G11C16/344 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/16 ,  G11C2211/5621

Abstract: A semiconductor memory device includes a memory cell array, data buffer, and column switch. The data buffer senses the potential of a bit line to determine data in a selected memory cell and hold readout data in a read. The data buffer detects both whether the whole data buffer holds “0” data and whether the whole data buffer holds “1” data. The column switch selects part of the data buffer and connects the part to a bus.

Abstract translation: 半导体存储器件包括存储单元阵列，数据缓冲器和列开关。 数据缓冲器检测位线的电位以确定所选择的存储单元中的数据并保持读取中的读出数据。 数据缓冲器检测整个数据缓冲器是否保持“0”数据以及整个数据缓冲器是否保持“1”数据。 列开关选择数据缓冲区的一部分，并将部件连接到总线。

公开(公告)号：US07085160B2

公开(公告)日：2006-08-01

申请号：US10958331

申请日：2004-10-06

Applicant: Hitoshi Shiga ,  Chin Hsi Lin

Inventor： Hitoshi Shiga ,  Chin Hsi Lin

IPC: G11C16/04

CPC classification number: G11C16/344 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/16 ,  G11C2211/5621

Abstract: A semiconductor memory device includes a memory cell array, data buffer, and column switch. The data buffer senses the potential of a bit line to determine data in a selected memory cell and hold readout data in a read. The data buffer detects both whether the whole data buffer holds “0” data and whether the whole data buffer holds “1” data. The column switch selects part of the data buffer and connects the part to a bus.

Abstract translation: 半导体存储器件包括存储单元阵列，数据缓冲器和列开关。 数据缓冲器检测位线的电位以确定所选择的存储单元中的数据并保持读取中的读出数据。 数据缓冲器检测整个数据缓冲器是否保持“0”数据以及整个数据缓冲器是否保持“1”数据。 列开关选择数据缓冲区的一部分，并将部件连接到总线。

公开(公告)号：US06175519B1

公开(公告)日：2001-01-16

申请号：US09359197

申请日：1999-07-22

Applicant: Tao Cheng Lu ,  Mam Tsung Wang ,  Chin Hsi Lin ,  Ful Long Ni

Inventor： Tao Cheng Lu ,  Mam Tsung Wang ,  Chin Hsi Lin ,  Ful Long Ni

IPC: G11C1606

CPC classification number: G11C16/0491 ,  G11C5/063

Abstract: In a virtual ground semiconductor memory device such as an EPROM or a Flash EPROM, a program disturb inhibited unit is operatively connected to a memory array. The memory array includes a plurality of metal virtual ground and bit lines, with at least two bit line selection transistors connected to each of the metal lines. The program disturb inhibited is connected to each virtual ground line and each bit line. In this structure, one metal pitch is connected to two buried diffusion lines. The program inhibited unit includes a plurality of program disturb inhibited transistors, wherein each transistor is connected between a virtual ground and a bit line. A DWL and a DWR dummy line are connected to control the plurality of program disturb inhibited transistors. By combining the program disturb inhibit unit with the memory array, a conventional array structure which has only been suitable for MROM applications can be applied to an EPROM or a Flash EEPROM, allowing the cell size to be reduced.

Abstract translation: 在诸如EPROM或闪存EPROM的虚拟地面半导体存储器件中，程序干扰抑制单元可操作地连接到存储器阵列。 存储器阵列包括多个金属虚拟接地和位线，其中至少两个位线选择晶体管连接到每个金属线。 禁止的程序干扰连接到每个虚拟接地线和每个位线。 在这种结构中，一个金属间距连接到两个掩埋的扩散线。 程序禁止单元包括多个编程干扰禁止晶体管，其中每个晶体管连接在虚拟地和位线之间。 连接DWL和DWR虚拟线以控制多个编程干扰被禁止的晶体管。 通过将编程干扰抑制单元与存储器阵列组合，仅适用于MROM应用的常规阵列结构可以应用于EPROM或闪速EEPROM，从而可以减小单元大小。

公开(公告)号：US06525361B1

公开(公告)日：2003-02-25

申请号：US09443964

申请日：1999-11-19

Applicant: Tao Cheng Lu ,  Chung Ju Chen ,  Hon Sui Lin ,  Mam Tsung Wang ,  Chin Hsi Lin ,  Ful Long Ni

Inventor： Tao Cheng Lu ,  Chung Ju Chen ,  Hon Sui Lin ,  Mam Tsung Wang ,  Chin Hsi Lin ,  Ful Long Ni

IPC: H01L27102

CPC classification number: H01L27/1126 ,  G11C11/56 ,  G11C11/5642 ,  G11C11/5692 ,  H01L27/112

Abstract: An asymmetric multilevel memory cell provides an inhibited source read current. The inhibited source read current dramatically reduces the likelihood of a cell type misread error for a memory array comprising multilevel cells. The method for fabricating the asymmetric multilevel memory cell comprises a source only implant, formation of a spacer on the drain side of the gate prior to source/drain implant, and the resultant formation of an offset region disposed between the channel and the drain. The offset region is not controlled by the gate voltage. The drain current at 1.5 volts is more than 3.5 times larger than the source current at 1.5 volts for spacer width of 0.12 micrometers. Asymmetric multilevel memory cells in a memory array, where the cells have a common source configuration, are accurately read in one direction because neighboring cells on the word line have substantially lower source current than the read cell drain current.

公开(公告)号：US06181604B2

公开(公告)日：2001-01-30

申请号：US09359073

申请日：1999-07-22

Applicant: Tao Cheng Lu ,  Wen Jer Tsai ,  Mam Tsung Wang ,  Chin Hsi Lin ,  Ful Long Ni

Inventor： Tao Cheng Lu ,  Wen Jer Tsai ,  Mam Tsung Wang ,  Chin Hsi Lin ,  Ful Long Ni

IPC: G11C1606

CPC classification number: G11C16/3427 ,  G11C11/5621 ,  G11C11/5628 ,  G11C16/0491 ,  G11C16/10 ,  G11C16/3418 ,  G11C2211/5621

Abstract: A method for programming a semiconductor memory device, such as an EPROM or a Flash EPROM, which combines the advantages of ramping down a source voltage with the advantages associated with increasing a gate voltage. A programming period is divided into a program disturbance inhibited period and a program period. The programming period is further divided into sub-program periods, with each sub-program period having a program disturbance and a program period. A wordline WL voltage may increase with each sub-program period to improve the programming speed. Also, the program disturbance period may only be performed for the first sub-program period. Each sub-program period may also include a verify period, in order to implement a program and verify technique suitable for programming multi-level Flash EPROMS.

Abstract translation: 一种用于编程诸如EPROM或闪存EPROM的半导体存储器件的方法，其结合了降低源电压的优点和与增加栅极电压相关联的优点。 编程周期分为程序禁止干扰期和程序周期。 编程周期进一步分为子程序周期，每个子程序周期都有程序干扰和程序周期。 字线WL电压可能随着每个子程序周期而增加，以提高编程速度。 此外，程序干扰周期可以仅在第一子程序周期执行。 每个子程序周期还可以包括验证周期，以便实现适合于编程多级闪存EPROMS的程序和验证技术。

公开(公告)号：US06046934A

公开(公告)日：2000-04-04

申请号：US229460

申请日：1999-01-12

Applicant: Chin Hsi Lin

Inventor： Chin Hsi Lin

IPC: G11C11/56 ,  G11C16/34 ,  G11C11/34

CPC classification number: G11C16/3459 ,  G11C11/5621 ,  G11C11/5628 ,  G11C16/34 ,  G11C16/3468 ,  G11C16/3481 ,  G11C16/08 ,  G11C2211/5621 ,  G11C2211/5624 ,  G11C2211/5645 ,  G11C8/14

Abstract: A method and device for programming multiple levels of voltage states in a memory cell. A program and verify memory cell device includes a memory cell coupled with at least one dummy cell, the devices sharing common drain, gate, and source nodes. The threshold voltage of each dummy cell is set to a target threshold level for programming the memory cell. A stair-step sequence of pulses is used to program and verify the memory cell. A constant current source can also be coupled between the source node and the ground. The programming steps for this device include applying a high voltage to the drain and gate nodes, and coupling the source to level while starting the program pulse, then establishing a constant current at the source to pull it from high to level, and then applying program and verify pulses at the memory cell gate. A self convergence memory cell device includes the parallel connected memory and dummy cells above, but with at least one current sensing device coupled between the dummy cell and the drain. The programming steps for this device include applying a high voltage to the drain and gate nodes, and coupling the source to level while starting the program pulse, then establishing a constant current at the source to pull it from high to level, and then using the current sensing device to pull down the drain when a certain dummy cell current is reached upon subsequent application of programming pulses.

Abstract translation: 一种用于对存储器单元中的多个电压状态进行编程的方法和装置。 程序和验证存储单元装置包括与至少一个虚拟单元耦合的存储单元，该单元共享共同的漏极，栅极和源极节点。 将每个虚拟单元的阈值电压设置为用于编程存储单元的目标阈值电平。 使用阶梯级的脉冲来对存储单元进行编程和验证。 恒流源也可以耦合在源节点和地之间。 该器件的编程步骤包括向漏极和栅极节点施加高电压，并在启动编程脉冲时将源耦合到电平，然后在源上建立恒定电流以将其从高电平拉高，然后应用程序 并在存储单元门上验证脉冲。 自会聚存储单元器件包括上述并联连接的存储器和虚拟单元，但是至少一个电流感测器件耦合在虚拟单元和漏极之间。 该器件的编程步骤包括向漏极和栅极节点施加高电压，并在启动编程脉冲时将源耦合到电平，然后在源极上建立恒定电流，将其从高电平拉高，然后使用 电流感测装置在随后施加编程脉冲时达到某个虚设电池电流时下拉漏极。