公开(公告)号：US07382652B2

公开(公告)日：2008-06-03

申请号：US11564887

申请日：2006-11-30

Applicant: Hitoshi Shiga ,  Chih-Hung Wang ,  Chin Hsi Lin

Inventor： Hitoshi Shiga ,  Chih-Hung Wang ,  Chin Hsi Lin

IPC: G11C16/04

CPC classification number: G11C16/344 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/16 ,  G11C2211/5621

Abstract: A semiconductor memory device includes a memory cell array, data buffer, and column switch. The data buffer senses the potential of a bit line to determine data in a selected memory cell and hold readout data in a read. The data buffer detects both whether the whole data buffer holds “0” data and whether the whole data buffer holds “1” data. The column switch selects part of the data buffer and connects the part to a bus.

Abstract translation: 半导体存储器件包括存储单元阵列，数据缓冲器和列开关。 数据缓冲器检测位线的电位以确定所选择的存储单元中的数据并保持读取中的读出数据。 数据缓冲器检测整个数据缓冲器是否保持“0”数据以及整个数据缓冲器是否保持“1”数据。 列开关选择数据缓冲区的一部分，并将部件连接到总线。

公开(公告)号：US20060284234A1

公开(公告)日：2006-12-21

申请号：US11154378

申请日：2005-06-15

Applicant: Tsung-Min Hsieh ,  Chien-Hsing Lee ,  Chin-Hsi Lin ,  Jhyy-Cheng Liou

Inventor： Tsung-Min Hsieh ,  Chien-Hsing Lee ,  Chin-Hsi Lin ,  Jhyy-Cheng Liou

IPC: H01L29/76

CPC classification number: H01L27/115 ,  H01L27/11521 ,  H01L27/11524

Abstract: A nonvolatile memory device, including composite gate structures formed on a substrate in series along a bit line (BL) direction. Each of the composite gate structures has a first storage gate, a second storage gate, and a selection gate between the two storage gates. Each of the composite gate structures is respectively coupled to two world line (WL) connection terminals at the two storage gates and a selection terminal at the selection gate. Each of the storage gates corresponds to a memory bit cell. Multiple doped regions are in the substrate between the composite gate structures. A first selection doped region are formed in the substrate and coupled between a BL connection terminal and a first edge one of the composite gate structure. A second selection doped region is formed in the substrate and coupled between a second edge one of the composite gate structures and a voltage terminal.

Abstract translation: 一种非易失性存储器件，包括沿着位线（BL）方向串联形成在衬底上的复合栅极结构。 复合栅极结构中的每一个在两个存储栅极之间具有第一存储栅极，第二存储栅极和选择栅极。 复合栅极结构中的每一个分别耦合到两个存储栅极处的两个世界线（WL）连接端子和选择栅极处的选择端子。 每个存储门对应于存储器位单元。 多个掺杂区域在复合栅极结构之间的衬底中。 第一选择掺杂区域形成在衬底中并且耦合在BL连接端子和复合栅极结构中的第一边缘之间。 第二选择掺杂区域形成在衬底中并且耦合在复合栅极结构之一的第二边缘和电压端子之间。

公开(公告)号：US20060013041A1

公开(公告)日：2006-01-19

申请号：US11233917

申请日：2005-09-23

Applicant: Chin-Hsi Lin

Inventor： Chin-Hsi Lin

IPC: G11C16/06 ,  G11C11/34 ,  G11C16/04

CPC classification number: G11C7/1039 ,  G11C7/18 ,  G11C7/22 ,  G11C16/28 ,  G11C17/12 ,  G11C17/123 ,  G11C2207/002

Abstract: The invention is directed to a via-mask read only memory (ROM) layout structure, including a dynamic random access memory (DRAM) like layout structure, serving as a main body structure and having an array of coding transistors. A grounding structure line is disposed over the source regions of the coding transistors. The grounding layer is located at a position, where capacitor areas are defined in a DRAM structure. A plurality of vias are corresponding to a portion of the coding transistors, for coupling the source regions with the grounding structure line. Each of the vias in the corresponding coding transistors represents a first binary data, and the coding transistors without the vias represent a second binary data.

Abstract translation: 本发明涉及一种通孔掩模只读存储器（ROM）布局结构，其包括用作主体结构并具有编码晶体管阵列的类似布局结构的动态随机存取存储器（DRAM）。 接地结构线设置在编码晶体管的源极区域上。 接地层位于电容器区域被限定在DRAM结构中的位置处。 多个通孔对应于编码晶体管的一部分，用于将源极区域与接地结构线耦合。 相应的编码晶体管中的每个通孔代表第一二进制数据，而没有通孔的编码晶体管表示第二二进制数据。

公开(公告)号：US06028790A

公开(公告)日：2000-02-22

申请号：US227024

申请日：1999-01-07

Applicant: Chin-Hsi Lin ,  Ful-Long Ni ,  Mam-Tsung Wang

Inventor： Chin-Hsi Lin ,  Ful-Long Ni ,  Mam-Tsung Wang

IPC: G11C16/10 ,  G11C16/30 ,  G11C16/00

CPC classification number: G11C16/30 ,  G11C16/10

Abstract: A method and apparatus for programming a non-volatile memory cell wherein the rate of current flowing through the cell is controlled via a current limiter coupled to the source node of the memory cell. The rate of current through the current limiter controls the programming current rate through the memory cell. The current limiter is controlled by an input which is dependant upon the setting of a current through an associated current mirror device. The current mirror current is controlled by a pre-defined input condition on a current source. The mirror current is used by a biasing circuit to generate a proportional input to the current limiter device. The current source thereby controls the current limiter rate. The current source can be formed from the same process as the memory cells and its output will thereby vary with the conductivity of the formed devices. This variation in the current source output, and hence the current limiter current, can be used to compensate for the comparable conductivity variations in the memory cells. The programming current rate can thereby be controlled, and can additionally be controlled according to process variations in the memory cell devices.

Abstract translation: 一种用于对非易失性存储单元进行编程的方法和装置，其中通过耦合到存储单元的源节点的限流器来控制流过单元的电流的速率。 通过限流器的电流速率控制通过存储单元的编程电流速率。 电流限制器由输入控制，该输入取决于通过相关联的电流镜装置的电流的设置。 电流镜电流由电流源上的预定义输入条件控制。 偏置电路使用镜电流来产生与限流器器件的比例输入。 因此，电流源控制电流限制器速率。 电流源可以由与存储单元相同的工艺形成，并且其输出将随着形成的器件的导电性而变化。 电流源输出中的这种变化以及因此的电流限制器电流可用于补偿存储器单元中可比较的电导率变化。 因此可以控制编程电流速率，并且可以根据存储单元装置中的工艺变化另外控制编程电流速率。

公开(公告)号：US5323804A

公开(公告)日：1994-06-28

申请号：US92820

申请日：1993-07-19

Applicant: Chin-Hsi Lin

Inventor： Chin-Hsi Lin

IPC: E03F5/04 ,  E03F5/042 ,  E03F7/06 ,  F16L5/00

CPC classification number: E03F5/0407 ,  E03F5/042 ,  E03F7/06 ,  E03F2005/0417 ,  Y10T137/6988 ,  Y10T137/7903

Abstract: An improved bug-proof and odor-proof draining outlet structure is particularly adapted for use on floors and is equipped with a pair of symmetric semi-circular blockage flaps that are pivotally fixed at the bottom periphery of the draining outlet and are one-way openable. At one side of each flap is disposed a counterweight so that as water is discharged via the blockage flaps, the same will be pushed opened, permitting water to be expelled out, and then automatically closed due to gravity exerted on the counterweights. Water is directly discharged into a duct without moving against the wall of the duct so as to make the discharge of the water in a more smooth and effective manner. Besides, the bottom periphery of the draining outlet is provided with a pair of supporting lugs each having a slot-like opening so that a pivot pin fixed to the underside of each blockage flap can be in snap engagement with each supporting lug with ease.

Abstract translation: 改进的防臭和防臭排水出口结构特别适用于地板，并配有一对对称的半圆形阻塞挡板，其可枢转地固定在排水口的底部周边，并且是单向可打开的 。 在每个翼片的一侧设置配重，使得当水通过阻塞片排出时，其将被推开，允许水被排出，然后由于重力施加在配重上而自动关闭。 水直接排放到管道中，而不会移动到管道的壁上，以便以更平稳和有效的方式排放水。 此外，排水出口的底部边缘设置有一对支撑凸耳，每个支撑凸耳具有槽状开口，使得固定到每个阻塞挡板的下侧的枢轴销可以容易地与每个支撑凸耳卡扣接合。

公开(公告)号：US20080225570A1

公开(公告)日：2008-09-18

申请号：US12128738

申请日：2008-05-29

Applicant: Chin-Hsi Lin ,  Chi-Ming Weng

Inventor： Chin-Hsi Lin ,  Chi-Ming Weng

IPC: G11C11/22 ,  G11C7/00

CPC classification number: G11C14/00 ,  G11C11/22

Abstract: An over-driven access method and device for ferroelectric memory. When accessing the data stored in a ferroelectric memory, the invention further provides an over-driven current to slightly reduce/raise the voltages in bit lines BL and BL′ to further enlarge the voltage difference therebetween after having raised the plate-line /bit-line voltage using the plate-line /bit-line driven method.

Abstract translation: 用于铁电存储器的过驱动访问方法和装置。 当访问存储在铁电存储器中的数据时，本发明还提供过驱动电流以稍微降低/升高位线BL和BL'中的电压，以在升高板线/位位线之后进一步扩大它们之间的电压差， 线路电压采用板线/位线驱动方式。

公开(公告)号：US07394678B2

公开(公告)日：2008-07-01

申请号：US11771048

申请日：2007-06-29

Applicant: Chin-Hsi Lin ,  Chi-Ming Weng

Inventor： Chin-Hsi Lin ,  Chi-Ming Weng

IPC: G11C11/22 ,  G11C7/00

CPC classification number: G11C14/00 ,  G11C11/22

Abstract: An over-driven access method and device for ferroelectric memory. When accessing the data stored in a ferroelectric memory, the invention further provides an over-driven current to slightly reduce/raise the voltages in bit lines BL and BL′ to further enlarge the voltage difference therebetween after having raised the plate-line/bit-line voltage using the plate-line/bit-line driven method.

公开(公告)号：US20070247891A1

公开(公告)日：2007-10-25

申请号：US11771048

申请日：2007-06-29

Applicant: Chin-Hsi Lin ,  Chi-Ming Weng

Inventor： Chin-Hsi Lin ,  Chi-Ming Weng

IPC: G11C11/22

CPC classification number: G11C14/00 ,  G11C11/22

Abstract: An over-driven access method and device for ferroelectric memory. When accessing the data stored in a ferroelectric memory, the invention further provides an over-driven current to slightly reduce/raise the voltages in bit lines BL and BL′ to further enlarge the voltage difference therebetween after having raised the plate-line/bit-line voltage using the plate-line/bit-line driven method.

公开(公告)号：US20060284240A1

公开(公告)日：2006-12-21

申请号：US11473578

申请日：2006-06-22

Applicant: Tsung-Min Hsieh ,  Chien-Hsing Lee ,  Chin-Hsi Lin ,  Jhyy-Cheng Liou

Inventor： Tsung-Min Hsieh ,  Chien-Hsing Lee ,  Chin-Hsi Lin ,  Jhyy-Cheng Liou

IPC: H01L29/788

CPC classification number: H01L27/115 ,  H01L27/11521 ,  H01L27/11524

Abstract: A nonvolatile memory device includes composite gate structures formed on a substrate in series along a bit line direction. The composite gate structure has a first storage gate structure, a second storage gate structure, and a selection gate between the two storage gate structures. Each of the composite gate structures is respectively coupled to two world line connection terminals at the two storage gate structures and a selection terminal at the selection gate. Each of the storage gate structures corresponds to a memory bit cell. Multiple doped regions are in the substrate between the composite gate structures. A first selection doped region are formed in the substrate and coupled between a BL connection terminal and a first edge one of the composite gate structure. A second selection doped region is formed in the substrate and coupled between a second edge one of the composite gate structures and a voltage terminal.

Abstract translation: 非易失性存储器件包括沿着位线方向串联地形成在衬底上的复合栅极结构。 复合栅极结构具有第一存储栅极结构，第二存储栅极结构和两个存储栅极结构之间的选择栅极。 复合栅极结构中的每一个分别耦合到两个存储栅极结构处的两个世界线连接端子和选择栅极处的选择端子。 每个存储门结构对应于存储器位单元。 多个掺杂区域在复合栅极结构之间的衬底中。 第一选择掺杂区域形成在衬底中并且耦合在BL连接端子和复合栅极结构中的第一边缘之间。 第二选择掺杂区域形成在衬底中并且耦合在复合栅极结构之一的第二边缘和电压端子之间。

公开(公告)号：US07119394B2

公开(公告)日：2006-10-10

申请号：US11297266

申请日：2005-12-07

Applicant: Tsung-Min Hsieh ,  Jhyy-Cheng Liou ,  Chien-Hsing Lee ,  Chin-Hsi Lin

Inventor： Tsung-Min Hsieh ,  Jhyy-Cheng Liou ,  Chien-Hsing Lee ,  Chin-Hsi Lin

IPC: H01L29/788

CPC classification number: G11C16/0491 ,  G11C16/0475 ,  H01L27/115 ,  H01L27/11568

Abstract: A structure of non-volatile memory has a plurality of buried bit lines in a substrate, extending along a first direction. Selection gate structure lines are located between the buried bit lines. A plurality of stack dielectric films on the both sides of the selection gate structure lines serving as a charge storage region, does not extend to the bit lines and a dielectric layer contacting a surface of substrate adjacent to stacked dielectric films. Word lines are over the substrate, wherein stacked dielectric films and a dielectric layer are interposed between WL and substrate on the region excluding the selection gate structure line, extending along a second direction different from the first direction. Since the charge storage layer does not completely cover between the selection gate structure lines and the bit lines, an additional control gate is formed.