公开(公告)号：US07161860B2

公开(公告)日：2007-01-09

申请号：US11115373

申请日：2005-04-27

申请人： Sung Joo Ha ,  Ho Youb Cho

发明人： Sung Joo Ha ,  Ho Youb Cho

IPC分类号： G11C7/00

CPC分类号： G11C7/12

摘要： A local input/output line precharge circuit of a semiconductor memory device comprises a precharge control unit, an equalization unit and a data output unit. The precharge control unit outputs a precharge control signal to precharge a pair of local input/output lines in response to a continuous write signal activated when a write operation continues. The equalization unit precharges and equalizing the pair of local input/output lines in response to the precharge control signal. The data output unit outputs data signals of a pair of global input/output lines to the pair of local input/output lines in response to output signal from the equalization unit. In the circuit, a local input/output line precharge operation is not performed at a continuous write mode, thereby reducing current consumption.

摘要翻译： 半导体存储器件的本地输入/输出线预充电电路包括预充电控制单元，均衡单元和数据输出单元。 预充电控制单元输出预充电控制信号，以便在写入操作继续时响应于激活的连续写入信号对一对本地输入/输出线进行预充电。 均衡单元响应于预充电控制信号对一对本地输入/输出线进行预充电和均衡。 数据输出单元响应于来自均衡单元的输出信号，将一对全局输入/输出线的数据信号输出到一对本地输入/输出线。 在该电路中，在连续写入模式下不执行局部输入/输出线预充电操作，从而减少电流消耗。

公开(公告)号：US07068549B2

公开(公告)日：2006-06-27

申请号：US10878755

申请日：2004-06-28

申请人： Ho Youb Cho

发明人： Ho Youb Cho

IPC分类号： G11C7/00

CPC分类号： G11C7/1066 ,  G11C7/1072 ,  G11C7/22 ,  G11C11/4076

摘要： Provided is directed to a circuit for generating a DQS signal in a semiconductor memory device which includes: a DQS data generation unit for generating a DQS preamble signal and a DQS data, signals earlier than a CAS latency; a DQS output control signal generation unit for generating a control signal to drive the DQS preamble signal out before the CAS latency and to drive the DQS data out after the CAS latency; a DQS driver for driving the DQS preamble signal and a rising data of the DQS data from the DQS data generation unit according to a rising clock of the DQS output control signal generation unit, and driving a falling data from the DQS data generation unit according to a falling clock of the DQS output control signal generation unit.

摘要翻译： 本发明提供一种用于在半导体存储器件中产生DQS信号的电路，该电路包括：用于产生DQS前导信号和DQS数据的DQS数据产生单元，该信号早于CAS延迟; DQS输出控制信号生成单元，用于在CAS等待时间之前产生驱动DQS前导码信号的控制信号，并在CAS等待时间之后驱动DQS数据; 根据DQS输出控制信号生成单元的上升时钟，驱动DQS前导码信号的DQS驱动器和来自DQS数据生成部的DQS数据的上升数据，根据DQS数据生成部的下降数据，根据 DQS输出控制信号发生单元的下降时钟。

公开(公告)号：US08767480B2

公开(公告)日：2014-07-01

申请号：US13492204

申请日：2012-06-08

申请人： Sang Oh Lim ,  Ho Youb Cho

发明人： Sang Oh Lim ,  Ho Youb Cho

IPC分类号： G11C7/00 ,  G11C8/00

CPC分类号： G11C16/06 ,  G11C16/32

摘要： A semiconductor memory device includes a count clock generation unit for generating a count clock in response to a clock signal and a dummy count clock, a column address generation unit for generating a column address in response to the count clock, and a Y decoder for sending data, stored in a page buffer unit, to a data line in response to the column address.

摘要翻译： 半导体存储器件包括：计数时钟生成单元，用于响应于时钟信号和虚拟计数时钟产生计数时钟;列地址生成单元，用于响应于计数时钟产生列地址;以及Y解码器，用于发送 存储在页面缓冲单元中的数据响应于列地址到数据行。

公开(公告)号：US06229747B1

公开(公告)日：2001-05-08

申请号：US09468784

申请日：1999-12-21

申请人： Ho Youb Cho ,  Jin Keun Oh

发明人： Ho Youb Cho ,  Jin Keun Oh

IPC分类号： G11C700

CPC分类号： G11C11/40615 ,  G11C11/406 ,  G11C2211/4068

摘要： A self-refresh apparatus for a semiconductor memory device is disclosed. According to the self-refresh apparatus, Data loss can be prevented by monitoring a leakage of memory cell data, activating a variable self-refresh signal in accordance with a signal resulted from the monitoring during a self-refresh mode, producing a refresh request signal when the self-refresh signal is activated and then refreshing all of memory cells. An unnecessary power consumption can be also prevented by variably performing the refresh operation in accordance with the retention time of cell data.

摘要翻译： 公开了一种用于半导体存储器件的自刷新装置。 根据自刷新装置，可以通过监视存储单元数据的泄漏，根据在自刷新模式期间的监视产生的信号来激活可变自刷新信号来防止数据丢失，产生刷新请求信号 当自刷新信号被激活然后刷新所有存储单元时。 还可以通过根据单元数据的保持时间可变地执行刷新操作来防止不必要的功耗。

公开(公告)号：US08300460B2

公开(公告)日：2012-10-30

申请号：US12826570

申请日：2010-06-29

申请人： Ho Youb Cho

发明人： Ho Youb Cho

IPC分类号： G11C11/34

CPC分类号： G11C16/0483 ,  G11C16/08 ,  G11C16/10 ,  G11C2216/14

摘要： A nonvolatile memory device comprises a page buffer unit comprising page buffers, each coupling first and second input and output (IO) lines and a latch circuit for outputting data together or coupling a sense node and the first or second I/O line together, in response to an operation mode; a Y decoder unit comprising decoders, each selecting one or more of the page buffers in response to address signals and outputting a first or second control signal to the selected page buffers in response to the operation mode; a mode selection unit outputting first and second operation selection signals for selecting the operation mode; and an I/O control unit comprising I/O control circuits, each detecting data, inputted and output through the first and second I/O lines, and outputting the detected data or coupling one of the first and second I/O lines to a data line.

摘要翻译： 非易失性存储器件包括页缓冲器单元，其包括页缓冲器，每个耦合第一和第二输入和输出线（IO）线和用于一起输出数据或将感测节点与第一或第二I / O线耦合在一起的锁存电路， 响应操作模式; Y解码器单元，包括解码器，每个解码器响应于地址信号而选择一个或多个寻呼缓冲器，并响应于操作模式向所选页缓冲器输出第一或第二控制信号; 模式选择单元，输出用于选择操作模式的第一和第二操作选择信号; 以及I / O控制单元，其包括I / O控制电路，每个检测数据通过第一和第二I / O线输入和输出，并输出检测到的数据或将第一和第二I / O线中的一个连接到 数据线。

公开(公告)号：US06720802B2

公开(公告)日：2004-04-13

申请号：US10178497

申请日：2002-06-24

申请人： Ho Youb Cho

发明人： Ho Youb Cho

IPC分类号： H03B100

CPC分类号： H03K19/09429

摘要： A data output buffer is disclosed that is capable of reducing the power consumption of a circuit utilizing low power consumption in such a way that a data output buffer driver of the data output buffer is turned off to place a data output signal at a HIGH impedance state during a deep power mode wherein all internal supply voltages used are in an OFF state. Therefore, the data output buffer can prevent a data contention in a data bus and shut off a current path to prevent unnecessary power consumption.

摘要翻译： 公开了一种数据输出缓冲器，其能够以使得数据输出缓冲器的数据输出缓冲器驱动器被关闭以将数据输出信号置于高阻抗状态的方式降低利用低功耗的电路的功耗 在其中使用的所有内部电源电压处于OFF状态的深度功率模式期间。 因此，数据输出缓冲器可以防止数据总线中的数据争用，并切断当前路径以防止不必要的功耗。

公开(公告)号：US20110249480A1

公开(公告)日：2011-10-13

申请号：US13085028

申请日：2011-04-12

申请人： Ho Youb Cho

发明人： Ho Youb Cho

IPC分类号： G11C15/00 ,  G11C29/04

CPC分类号： G11C29/789 ,  G11C15/00

摘要： Disclosed is a nonvolatile memory device including a memory cell array including main and redundant memory cells, content addressable memory cells configured to store a defective column address corresponding to a defective memory cell among the main cells, and a repair controller configured to compare the defective column address with an input address to generate a matching control signal and generate a redundancy check-enable signal when the defective column address is inputted as the input address and configured to generate a repair control signal in response to the matching control signal and the redundancy check-enable signal.

摘要翻译： 公开了一种非易失性存储装置，包括：包括主存储单元和冗余存储单元的存储单元阵列;内容可寻址存储单元，被配置为存储与主单元中的有缺陷存储单元相对应的缺陷列地址;以及修补控制器， 具有输入地址以产生匹配控制信号，并且当缺陷列地址被输入作为输入地址并且被配置为响应于匹配控制信号和冗余校验信号产生修复控制信号时产生冗余校验使能信号， 启用信号。

公开(公告)号：US07230864B2

公开(公告)日：2007-06-12

申请号：US11606928

申请日：2006-12-01

申请人： Sung Joo Ha ,  Ho Youb Cho

发明人： Sung Joo Ha ,  Ho Youb Cho

IPC分类号： G11C7/00

CPC分类号： G11C7/222 ,  G11C7/22 ,  G11C8/18 ,  G11C11/4076

摘要： A circuit for generating a data strobe signal of a semiconductor memory device comprises a plurality of internal clock delay units, a selecting control unit and a pulse generating unit. The plurality of internal clock delay units delay an internal clock signal in response to a plurality of CAS latency signal. The selecting control unit logically combines a data latch control signal to latch input data with output signals from the plurality of internal clock delay units. The pulse generating unit generates the data strobe signal having a predetermined pulse in response to an output signal from the selecting control unit. In the circuit, a tDQSS margin is regulated depending on change of tCK of an operating frequency in response to a CAS latency signal.

公开(公告)号：US08923051B2

公开(公告)日：2014-12-30

申请号：US13171783

申请日：2011-06-29

申请人： Ho Youb Cho

发明人： Ho Youb Cho

IPC分类号： G11C7/20 ,  G11C7/10 ,  G11C16/06 ,  G11C16/26 ,  G11C16/10

CPC分类号： G11C7/1021 ,  G11C7/20

摘要： A semiconductor memory apparatus includes: a memory block including first and second planes; and a reset signal generator configured to generate a first reset signal by logically combining a first plane selection signal and a control pulse signal which pulses after a first programming setup pulse signal pulses during a first programming command cycle, and generate a second reset signal by logically combining a second plane selection signal and the control pulse signal which again pulses after a second programming setup pulse signal pulses during a second programming command cycle after the first programming command cycle. A plurality of first page buffers allocated to the first plane are reset in response to the first reset signal, and a plurality of second page buffers allocated to the second plane are reset in response to the second reset signal.

摘要翻译： 一种半导体存储装置，包括：包括第一和第二平面的存储块; 以及复位信号发生器，被配置为通过在第一编程命令周期期间逻辑组合第一平面选择信号和在第一编程设置脉冲信号脉冲之后的脉冲的控制脉冲信号来产生第一复位信号，并且通过逻辑地产生第二复位信号 组合第二平面选择信号和在第一编程命令循环之后的第二编程命令周期期间在第二编程设置脉冲信号脉冲之后再次脉冲的控制脉冲信号。 分配给第一平面的多个第一页缓冲器响应于第一复位信号被复位，并且响应于第二复位信号复位分配给第二平面的多个第二页缓冲器。

公开(公告)号：US07869295B2

公开(公告)日：2011-01-11

申请号：US12535827

申请日：2009-08-05

申请人： Ho Youb Cho

发明人： Ho Youb Cho

IPC分类号： G11C7/02

CPC分类号： G11C7/065 ,  G11C7/08 ,  G11C2207/065

摘要： A semiconductor memory apparatus includes a sense amplifier that receives a driving voltage through a sense amplifier power supply input terminal and detects and amplifies a difference between signals that are supplied to two input lines, a sense amplifier voltage supply unit that supplies a driving voltage and an overdriving voltage higher than the driving voltage to the sense amplifier through the sense amplifier power supply input terminal using a power supply voltage, and a driving voltage control unit that maintains a driving voltage level of the sense amplifier power supply input terminal in response to the level of the power supply voltage, after a voltage of the sense amplifier power supply input terminal is elevated to a power supply level responding to the overdriving voltage in order to perform the overdriving operation.

摘要翻译： 半导体存储装置包括读出放大器，其通过读出放大器电源输入端子接收驱动电压，并检测并放大提供给两条输入线的信号之间的差异;提供驱动电压的读出放大器电压供给单元， 通过使用电源电压的感测放大器电源输入端子将高于通过感测放大器的驱动电压的过驱动电压，以及驱动电压控制单元，其响应于电平维持感测放大器电源输入端子的驱动电压电平 的电源电压，在感测放大器电源输入端子的电压升高到响应过驱动电压的电源电平以执行过驱动操作之后。