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    Memory devices that perform masked write operations and methods of operating the same
    1.
    发明授权
    Memory devices that perform masked write operations and methods of operating the same 有权
    执行屏蔽写操作的内存设备及其操作方法

    公开(公告)号：US09588840B2

    公开(公告)日：2017-03-07

    申请号：US14225686

    申请日：2014-03-26

    申请人： Hoi-ju Chung ,  Chul-sung Park ,  Tae-young Oh ,  Jang-woo Ryu ,  Chan-yong Lee ,  Tae-seong Jang ,  Gong-heum Han

    发明人： Hoi-ju Chung ,  Chul-sung Park ,  Tae-young Oh ,  Jang-woo Ryu ,  Chan-yong Lee ,  Tae-seong Jang ,  Gong-heum Han

    IPC分类号： G06F11/10 ,  G06F11/32

    CPC分类号： G06F11/1048 ,  G06F11/1008 ,  G06F11/1068 ,  G06F11/1072 ,  G06F11/1076

    摘要： A method of operating a memory device includes: generating an internal read command in response to a received masked write command, the internal read command being generated one of (i) during a write latency associated with the received masked write command, (ii) after receipt of a first bit of masked write data among a plurality of bits of masked write data, and (iii) in synchronization with a rising or falling edge of a clock signal received with an address signal corresponding to the masked write command; reading, in response to the internal read command, a plurality of bits of data stored in a plurality of memory cells, the plurality of memory cells corresponding to the address signal; and storing, in response to an internal write command, the plurality of bits of masked write data in the plurality of memory cells.

    摘要翻译： 一种操作存储器件的方法包括：响应于接收到的屏蔽写入命令产生内部读取命令，内部读取命令被生成（i）在与所接收的被屏蔽写入命令相关联的写入延迟期间，（ii）之后 在多个屏蔽写入数据位之间接收第一位掩蔽写入数据，以及（iii）与用与掩蔽写入命令对应的地址信号接收的时钟信号的上升沿或下降沿同步; 响应于所述内部读取命令，读取存储在多个存储器单元中的多个位数据，所述多个存储器单元对应于所述地址信号; 以及响应于内部写入命令，在所述多个存储器单元中存储所述多个掩码写入数据位。

    Memory controller, memory system including the memory controller, and operating method performed by the memory controller
    2.
    发明申请
    Memory controller, memory system including the memory controller, and operating method performed by the memory controller 有权
    存储器控制器，包括存储器控制器的存储器系统和由存储器控制器执行的操作方法

    公开(公告)号：US20140157045A1

    公开(公告)日：2014-06-05

    申请号：US14096824

    申请日：2013-12-04

    申请人： Hyun-joong Kim ,  Tae-young Oh

    发明人： Hyun-joong Kim ,  Tae-young Oh

    IPC分类号： G06F11/07

    CPC分类号： G11C29/76 ,  G06F11/073

    摘要： Provided are a memory controller, a memory system including the memory controller, and an operating method performed by the memory controller. The operating method includes operations of queuing a first command in a first queue, detecting a fail of a first address that corresponds to the first command, when the first address is determined as a fail address, queuing a second address and a second command in the first queue, wherein the second address is obtained by remapping the first address and the second command corresponds to the second address, and outputting the second command and the second address from the first queue.

    摘要翻译： 提供了存储器控制器，包括存储器控制器的存储器系统和由存储器控制器执行的操作方法。 操作方法包括在第一队列中排队第一命令，检测到与第一命令相对应的第一地址的失败的操作，当第一地址被确定为故障地址时，排队第二地址和第二命令中的第二命令 第一队列，其中通过重新映射第一地址获得第二地址，并且第二命令对应于第二地址，并且从第一队列输出第二命令和第二地址。