公开(公告)号：US08811111B2

公开(公告)日：2014-08-19

申请号：US12950028

申请日：2010-11-19

Applicant: Si-hong Kim ,  Young-hyun Jun ,  Kwnag-Il Park

Inventor： Si-hong Kim ,  Young-hyun Jun ,  Kwnag-Il Park

IPC: G11C8/18 ,  G11C7/22

CPC classification number: G11C7/225 ,  G06F1/06 ,  G11C7/02 ,  G11C7/1078 ,  G11C7/109 ,  G11C7/22 ,  G11C7/222 ,  G11C11/4076 ,  G11C11/4093

Abstract: A memory device comprising: at least one bank of memory cells that receives a first clock for clocking commands and a second clock for clocking data, wherein the second clock is activated based on a first command and deactivated based on a second command. The memory device further including a clock activation circuit configured to generate an enable signal based on the first command and a disable signal based on the second command, and a clock generator configured to generate the second clock based on a reference clock upon receipt of the enable signal.

Abstract translation: 一种存储器件，包括：至少一组存储器单元，其接收用于计时命令的第一时钟和用于计时数据的第二时钟，其中所述第二时钟基于第一命令而被激活，并且基于第二命令被去激活。 所述存储装置还包括时钟激活电路，所述时钟激活电路经配置以基于所述第一命令生成使能信号和基于所述第二命令的禁用信号;以及时钟发生器，被配置为在接收到所述使能时基于参考时钟生成所述第二时钟 信号。

公开(公告)号：US20110144912A1

公开(公告)日：2011-06-16

申请号：US12962973

申请日：2010-12-08

Applicant: Sung Jong Lee ,  Seung Keon Lee ,  Si Hong Kim

Inventor： Sung Jong Lee ,  Seung Keon Lee ,  Si Hong Kim

IPC: G08G3/02 ,  G08G3/00

CPC classification number: G08G3/00 ,  G08G3/02

Abstract: The present invention relates to a system for safety of a vessel and a method for safety of the vessel, and more particularly, to a system for safety of a vessel and a method for safety of the vessel using a mobile terminal device. According to the exemplary embodiment of the present invention, it is possible to provide a vessel collision preventing function which is available only in high-price exclusive marine equipment by utilizing a radio communication function and a location tracking function of a mobile terminal device even to small and medium-sized vessels and furthermore, rapidly and accurately display a vessel which is in a collision risk and allow a user to specifically recognize a collision preventing alarm so as to prevent collisions of the vessels.

Abstract translation: 本发明涉及一种用于船舶的安全性的系统和船舶的安全性方法，更具体地，涉及一种用于船舶安全的系统和使用移动终端设备的船舶的安全方法。 根据本发明的示例性实施例，可以通过利用移动终端设备的无线电通信功能和位置跟踪功能甚至小型提供仅在高价格专用船用设备中可用的船舶防撞功能 另外，能够快速，准确地显示碰撞风险的容器，能够特别识别防撞报警器，以防止容器的碰撞。

公开(公告)号：US20060145894A1

公开(公告)日：2006-07-06

申请号：US11198596

申请日：2005-08-04

Applicant: Si-Hong Kim ,  Sang-Sic Yoon

Inventor： Si-Hong Kim ,  Sang-Sic Yoon

IPC: H03M7/00

CPC classification number: G11C29/023 ,  G11C7/22 ,  G11C7/222 ,  G11C11/4076 ,  G11C29/02 ,  G11C29/50012

Abstract: An apparatus for controlling a latency in a synchronous semiconductor device. The apparatus includes a first counting block for counting a cycle of a first clock signal to thereby generate a first binary code; a second counting block for counting a cycle of a second clock signal to thereby generate a second binary code. The second clock signal is obtained by delaying the first clock signal by a predetermined delay amount, A code comparison block stores the second binary code in response to a command and compares the first binary code with the second binary code to thereby generate a latency control signal.

公开(公告)号：US20110309468A1

公开(公告)日：2011-12-22

申请号：US13088442

申请日：2011-04-18

Applicant: Tae-young Oh ,  Kwang-il Park ,  Seung-jun Bae ,  Yun-seok Yang ,  Young-soo Sohn ,  Si-hong Kim

Inventor： Tae-young Oh ,  Kwang-il Park ,  Seung-jun Bae ,  Yun-seok Yang ,  Young-soo Sohn ,  Si-hong Kim

IPC: H01L23/58 ,  H01L21/58

CPC classification number: H01L25/0657 ,  H01L24/16 ,  H01L24/94 ,  H01L25/50 ,  H01L2224/0557 ,  H01L2224/06131 ,  H01L2224/06135 ,  H01L2225/06541 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01004 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/30105 ,  H01L2224/05552

Abstract: A semiconductor chip package includes a substrate, a first layer disposed on the substrate and a second layer substantially similar to and disposed on the first layer. The first layer has a first input/output (I/O) circuit, a first through-via connected to the first input/output (I/O) circuit and a second through-via that is not connected to the first I/O circuit. The second layer has a second I/O circuit, a third through-via connected to the second I/O circuit and a fourth through-via that is not connected to the second I/O circuit. The first through-via is connected to the fourth through-via, and the second through-via is connected to the third through-via. The package maybe fabricated by stacking the layers, and changing the orientation of the second layer relative to the first to ensure that the first through-via is connected to the fourth through-via, and the second through-via is connected to the third through-via.

Abstract translation: 半导体芯片封装包括衬底，设置在衬底上的第一层和与第一层基本相似并且布置在第一层上的第二层。 第一层具有第一输入/输出（I / O）电路，连接到第一输入/输出（I / O）电路的第一通孔和未连接到第一I / O的第二通孔 电路。 第二层具有第二I / O电路，连接到第二I / O电路的第三通孔和未连接到第二I / O电路的第四通孔。 第一通孔连接到第四通孔，第二通孔连接到第三通孔。 封装可以通过堆叠层制造，并且相对于第一层改变第二层的取向以确保第一通孔连接到第四通孔，而第二通孔连接到第三通孔 -通过。

公开(公告)号：US20110292742A1

公开(公告)日：2011-12-01

申请号：US13085776

申请日：2011-04-13

Applicant: Tae-Young Oh ,  Kwang-il Park ,  Yun-Seok Yang ,  Young-Soo Sohn ,  Si-Hong Kim ,  Seung-Jun Bae

Inventor： Tae-Young Oh ,  Kwang-il Park ,  Yun-Seok Yang ,  Young-Soo Sohn ,  Si-Hong Kim ,  Seung-Jun Bae

IPC: G11C7/10 ,  H01L23/48

CPC classification number: G11C29/702 ,  G11C7/10 ,  H01L22/22 ,  H01L25/0657 ,  H01L25/18 ,  H01L2224/16 ,  H01L2225/06541

Abstract: A stacked semiconductor memory device according to the inventive concepts may include a plurality of memory chips stacked above a processor chip, a plurality of TSVs, and I/O buffers. The TSVs may pass through the memory chips and are connected to the processor chip. I/O buffers may be coupled between all or part of the memory chips and the TSVs and may be selectively activated on the basis of defective states of the TSVs.

Abstract translation: 根据本发明构思的叠层半导体存储器件可以包括堆叠在处理器芯片上方的多个存储器芯片，多个TSV和I / O缓冲器。 TSV可以通过存储器芯片并且连接到处理器芯片。 I / O缓冲器可以耦合在所有或部分存储器芯片和TSV之间，并且可以基于TSV的故障状态来选择性地激活。

公开(公告)号：US06650581B2

公开(公告)日：2003-11-18

申请号：US10128393

申请日：2002-04-23

Applicant: Sang Hoon Hong ,  Si Hong Kim

Inventor： Sang Hoon Hong ,  Si Hong Kim

IPC: G11C700

CPC classification number: G11C29/028 ,  G11C11/401 ,  G11C29/14 ,  G11C29/50 ,  G11C29/50012

Abstract: A semiconductor memory device and a method for testing the same which optimizes operation conditions by detecting a test cell that may easily fail in a test among the memory cells passing a burn-in test, and detecting the worst operation conditions by performing the test on the test cell. The device and method reduce power consumption in a refresh or active operation. According to the device and method set forth, a test unit tests a test cell, controls operation conditions of the semiconductor memory device according to the test result, and outputs the operation conditions. A driving unit drives the semiconductor memory device using the operation conditions controlled by the test unit.

Abstract translation: 一种半导体存储器件及其测试方法，其通过检测在通过老化测试的存储器单元中的测试中容易失败的测试单元来优化操作条件，并且通过对所述测试单元进行测试来检测最差的操作条件 测试单元。 该设备和方法在刷新或主动操作中降低功耗。 根据所述的装置和方法，测试单元测试测试单元，根据测试结果控制半导体存储器件的操作条件，并输出操作条件。 驱动单元使用由测试单元控制的操作条件驱动半导体存储器件。

公开(公告)号：US08553471B2

公开(公告)日：2013-10-08

申请号：US13239478

申请日：2011-09-22

Applicant: Si-Hong Kim ,  Seung-Jun Bae ,  Jin-Il Lee ,  Kwang-Il Park

Inventor： Si-Hong Kim ,  Seung-Jun Bae ,  Jin-Il Lee ,  Kwang-Il Park

IPC: G11C7/10 ,  G11C7/00

CPC classification number: G11C7/1057 ,  G11C29/022 ,  G11C29/028 ,  G11C2207/2254

Abstract: A data output buffer includes a driving unit and a control unit. The driving unit selectively performs a termination operation that provides a termination impedance to a transmission line coupled to an external pin, and a driving operation that provides a drive impedance to the transmission line while outputting read data. The control unit adjusts a value of the termination impedance and a value of the drive impedance based on an output voltage at the external pin during a termination mode, and controls the driving unit to selectively perform one of the termination operation and the driving operation during a driving mode.

Abstract translation: 数据输出缓冲器包括驱动单元和控制单元。 驱动单元选择性地执行向耦合到外部引脚的传输线提供终止阻抗的终止操作，以及在输出读取数据的同时向传输线提供驱动阻抗的驱动操作。 控制单元在终端模式期间根据外部引脚的输出电压来调整终端阻抗的值和驱动阻抗的值，并且控制驱动单元选择性地执行终止操作和驱动操作之一 驾驶模式。

公开(公告)号：US08342747B2

公开(公告)日：2013-01-01

申请号：US12694624

申请日：2010-01-27

Applicant: Si-Hong Kim ,  Kwang-Il Park ,  Hyun-Joong Kim

Inventor： Si-Hong Kim ,  Kwang-Il Park ,  Hyun-Joong Kim

IPC: G01K7/14

CPC classification number: G01K1/02 ,  G01K7/32 ,  G01K2219/00

Abstract: A temperature sensing circuit of a semiconductor device includes a code signal generator, a comparator, a reference clock generator and a final temperature code signal generator. The code signal generator is configured to output a first count signal having an increase rate that varies according to a change in temperature. The comparator is configured to receive the first count signal and a control signal, compare the first count signal with the control signal and output a comparison signal. The reference clock generator is configured to generate a reference clock having a uniform period regardless of the change in temperature during an activation period of the comparison signal. The final temperature code signal generator is configured to count pulses of the reference clock, generate a second count signal, modify the second count signal using an offset value, and output the modified second count signal as a final temperature code signal.

Abstract translation: 半导体器件的温度检测电路包括代码信号发生器，比较器，参考时钟发生器和最终温度代码信号发生器。 代码信号发生器被配置为输出具有根据温度变化而变化的增加率的第一计数信号。 比较器被配置为接收第一计数信号和控制信号，将第一计数信号与控制信号进行比较并输出比较信号。 参考时钟发生器被配置为在比较信号的激活周期期间生成具有均匀周期的参考时钟，而不管温度变化。 最终温度代码信号发生器被配置为对参考时钟的脉冲进行计数，产生第二计数信号，使用偏移值修改第二计数信号，并输出修改的第二计数信号作为最终温度代码信号。

公开(公告)号：US07994813B2

公开(公告)日：2011-08-09

申请号：US12719953

申请日：2010-03-09

Applicant: Young-Hoon Sohn ,  Kwang-Il Park ,  Yong-Gwon Jeong ,  Si-Hong Kim

Inventor： Young-Hoon Sohn ,  Kwang-Il Park ,  Yong-Gwon Jeong ,  Si-Hong Kim

IPC: H03K19/0175

CPC classification number: H04L25/0278

Abstract: A semiconductor device includes a plurality of pads, where an external reference resistor is connected to a first one of the pads, an impedance calibrating unit configured to generate an impedance calibration code corresponding to an impedance of the reference resistor and output the impedance calibration code to a code transmitting line during a normal operating mode, and an impedance matching unit configured to perform an impedance matching operation in response to the impedance calibration code during the normal operating mode. The impedance calibrating unit is configured to output a test code to the code transmitting line in response to a test signal during a test operating mode. The impedance matching unit is configured to serialize the test code to output the serialized test code to each of the other pads in response to the test signal during the test operating mode.

Abstract translation: 半导体器件包括多个焊盘，其中外部参考电阻器连接到焊盘的第一焊盘，阻抗校准单元被配置为产生对应于参考电阻器的阻抗的阻抗校准代码，并将阻抗校准代码输出到 在正常操作模式期间的代码传输线，以及阻抗匹配单元，被配置为在正常操作模式期间响应于阻抗校准码执行阻抗匹配操作。 阻抗校准单元被配置为在测试操作模式期间响应于测试信号将测试代码输出到代码传输线。 阻抗匹配单元被配置为串行化测试代码，以在测试操作模式期间响应于测试信号将串行测试代码输出到每个其它焊盘。

公开(公告)号：US20100189160A1

公开(公告)日：2010-07-29

申请号：US12694624

申请日：2010-01-27

Applicant: Si-Hong Kim ,  Kwang-Il Park ,  Hyun-Joong Kim

Inventor： Si-Hong Kim ,  Kwang-Il Park ,  Hyun-Joong Kim

IPC: G01K7/00

CPC classification number: G01K1/02 ,  G01K7/32 ,  G01K2219/00

Abstract: A temperature sensing circuit of a semiconductor device includes a code signal generator, a comparator, a reference clock generator and a final temperature code signal generator. The code signal generator is configured to output a first count signal having an increase rate that varies according to a change in temperature. The comparator is configured to receive the first count signal and a control signal, compare the first count signal with the control signal and output a comparison signal. The reference clock generator is configured to generate a reference clock having a uniform period regardless of the change in temperature during an activation period of the comparison signal. The final temperature code signal generator is configured to count pulses of the reference clock, generate a second count signal, modify the second count signal using an offset value, and output the modified second count signal as a final temperature code signal.

Abstract translation: 半导体器件的温度检测电路包括代码信号发生器，比较器，参考时钟发生器和最终温度代码信号发生器。 代码信号发生器被配置为输出具有根据温度变化而变化的增加率的第一计数信号。 比较器被配置为接收第一计数信号和控制信号，将第一计数信号与控制信号进行比较并输出比较信号。 参考时钟发生器被配置为在比较信号的激活周期期间生成具有均匀周期的参考时钟，而不管温度变化。 最终温度代码信号发生器被配置为对参考时钟的脉冲进行计数，产生第二计数信号，使用偏移值修改第二计数信号，并输出修改的第二计数信号作为最终温度代码信号。