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    Memory devices that perform masked write operations and methods of operating the same
    1.
    发明授权
    Memory devices that perform masked write operations and methods of operating the same 有权
    执行屏蔽写操作的内存设备及其操作方法

    公开(公告)号：US09588840B2

    公开(公告)日：2017-03-07

    申请号：US14225686

    申请日：2014-03-26

    申请人： Hoi-ju Chung ,  Chul-sung Park ,  Tae-young Oh ,  Jang-woo Ryu ,  Chan-yong Lee ,  Tae-seong Jang ,  Gong-heum Han

    发明人： Hoi-ju Chung ,  Chul-sung Park ,  Tae-young Oh ,  Jang-woo Ryu ,  Chan-yong Lee ,  Tae-seong Jang ,  Gong-heum Han

    IPC分类号： G06F11/10 ,  G06F11/32

    CPC分类号： G06F11/1048 ,  G06F11/1008 ,  G06F11/1068 ,  G06F11/1072 ,  G06F11/1076

    摘要： A method of operating a memory device includes: generating an internal read command in response to a received masked write command, the internal read command being generated one of (i) during a write latency associated with the received masked write command, (ii) after receipt of a first bit of masked write data among a plurality of bits of masked write data, and (iii) in synchronization with a rising or falling edge of a clock signal received with an address signal corresponding to the masked write command; reading, in response to the internal read command, a plurality of bits of data stored in a plurality of memory cells, the plurality of memory cells corresponding to the address signal; and storing, in response to an internal write command, the plurality of bits of masked write data in the plurality of memory cells.

    摘要翻译： 一种操作存储器件的方法包括：响应于接收到的屏蔽写入命令产生内部读取命令，内部读取命令被生成（i）在与所接收的被屏蔽写入命令相关联的写入延迟期间，（ii）之后 在多个屏蔽写入数据位之间接收第一位掩蔽写入数据，以及（iii）与用与掩蔽写入命令对应的地址信号接收的时钟信号的上升沿或下降沿同步; 响应于所述内部读取命令，读取存储在多个存储器单元中的多个位数据，所述多个存储器单元对应于所述地址信号; 以及响应于内部写入命令，在所述多个存储器单元中存储所述多个掩码写入数据位。

    MEMORY DEVICES THAT PERFORM MASKED WRITE OPERATIONS AND METHODS OF OPERATING THE SAME
    2.
    发明申请
    MEMORY DEVICES THAT PERFORM MASKED WRITE OPERATIONS AND METHODS OF OPERATING THE SAME 有权
    执行掩蔽写操作的记忆设备及其操作方法

    公开(公告)号：US20140317470A1

    公开(公告)日：2014-10-23

    申请号：US14225686

    申请日：2014-03-26

    申请人： Hoi-ju CHUNG ,  Chul-sung PARK ,  Tae-young OH ,  Jang-woo RYU ,  Chan-yong LEE ,  Tae-seong JANG ,  Gong-heum HAN

    发明人： Hoi-ju CHUNG ,  Chul-sung PARK ,  Tae-young OH ,  Jang-woo RYU ,  Chan-yong LEE ,  Tae-seong JANG ,  Gong-heum HAN

    IPC分类号： G06F11/10

    CPC分类号： G06F11/1048 ,  G06F11/1008 ,  G06F11/1068 ,  G06F11/1072 ,  G06F11/1076

    摘要： A method of operating a memory device includes: generating an internal read command in response to a received masked write command, the internal read command being generated one of (i) during a write latency associated with the received masked write command, (ii) after receipt of a first bit of masked write data among a plurality of bits of masked write data, and (iii) in synchronization with a rising or falling edge of a clock signal received with an address signal corresponding to the masked write command; reading, in response to the internal read command, a plurality of bits of data stored in a plurality of memory cells, the plurality of memory cells corresponding to the address signal; and storing, in response to an internal write command, the plurality of bits of masked write data in the plurality of memory cells.

    摘要翻译： 一种操作存储器件的方法包括：响应于接收到的屏蔽写入命令产生内部读取命令，内部读取命令被生成（i）在与所接收的被屏蔽写入命令相关联的写入延迟期间，（ii）之后 在多个屏蔽写入数据位之间接收第一位掩蔽写入数据，以及（iii）与用与掩蔽写入命令对应的地址信号接收的时钟信号的上升沿或下降沿同步; 响应于所述内部读取命令，读取存储在多个存储器单元中的多个位数据，所述多个存储器单元对应于所述地址信号; 以及响应于内部写入命令，在所述多个存储器单元中存储所述多个掩码写入数据位。

    Memory devices having controllers that divide command signals into two signals and systems including such memory devices
    3.
    发明授权
    Memory devices having controllers that divide command signals into two signals and systems including such memory devices 有权
    具有将命令信号分成两个信号的控制器的存储器件和包括这种存储器件的系统

    公开(公告)号：US08576644B2

    公开(公告)日：2013-11-05

    申请号：US13348672

    申请日：2012-01-12

    申请人： Seong Hyun Jeon ,  Hoi Ju Chung ,  Jung Sunwoo

    发明人： Seong Hyun Jeon ,  Hoi Ju Chung ,  Jung Sunwoo

    IPC分类号： G11C7/00

    CPC分类号： G11C7/1006 ,  G06F11/1048 ,  G06F2213/0038 ,  G11C7/109 ,  G11C7/22 ,  G11C2029/0411

    摘要： A memory device using error correcting code and a system including the same are provided. The memory device includes a memory cell array including a plurality of bit lines and a plurality of memory cells; an access block for accessing the memory cell array; and a controller block for receiving a first operation command signal, dividing the first operation command signal into at least two paths pulse signals corresponding to at least two paths, based on a pre-determined criterion, and then supplying the at least two path pulse signals to the access block. The access block operates based on an output signal of the controller block.

    摘要翻译： 提供了使用纠错码的存储装置和包括该存储装置的系统。 存储器件包括一个包括多个位线和多个存储单元的存储单元阵列; 访问所述存储单元阵列的访问块; 以及控制器块，用于接收第一操作命令信号，基于预定准则将第一操作命令信号划分为与至少两个路径相对应的至少两个路径脉冲信号，然后提供至少两个路径脉冲信号 到访问块。 访问块基于控制器块的输出信号进行操作。

    MEMORY DEVICE HAVING ERROR NOTIFICATION FUNCTION
    5.
    发明申请
    MEMORY DEVICE HAVING ERROR NOTIFICATION FUNCTION 有权
    具有错误通知功能的存储器

    公开(公告)号：US20160055056A1

    公开(公告)日：2016-02-25

    申请号：US14729656

    申请日：2015-06-03

    申请人： Jong-Pil SON ,  Chul-Woo PARK ,  Seong-Jin JANG ,  Hoi-Ju CHUNG ,  Sang-Uhn CHA

    发明人： Jong-Pil SON ,  Chul-Woo PARK ,  Seong-Jin JANG ,  Hoi-Ju CHUNG ,  Sang-Uhn CHA

    IPC分类号： G06F11/10 ,  G11C29/52

    CPC分类号： G06F11/1008 ,  G06F11/1004 ,  G06F11/1024 ,  G06F11/1068 ,  G06F11/1666 ,  G11C2029/0411

    摘要： A memory device having an error notification function includes an error correction code (ECC) engine detecting and correcting an error bit by performing an ECC operation on data of the plurality of memory cells, and an error notifying circuit configured to output an error signal according to the ECC operation. The ECC engine outputs error information corresponding to the error bit corresponding to a particular address corrected by the ECC operation. The error notifying circuit may output the error signal when the particular address is not the same as any one of existing one or more failed addresses.

    摘要翻译： 具有错误通知功能的存储装置包括通过对多个存储单元的数据执行ECC操作来检测和校正错误位的纠错码（ECC）引擎，以及错误通知电路，配置为根据 ECC操作。 ECC引擎输出与通过ECC操作校正的特定地址相对应的错误位对应的错误信息。 当特定地址与现有一个或多个故障地址中的任一个不同时，错误通知电路可以输出错误信号。

    Memory devices including selective RWW and RMW decoding
    6.
    发明授权
    Memory devices including selective RWW and RMW decoding 有权
    存储器件包括选择性RWW和RMW解码

    公开(公告)号：US08848465B2

    公开(公告)日：2014-09-30

    申请号：US13532911

    申请日：2012-06-26

    申请人： Seo-Hee Kim ,  Seong-Hyun Jeon ,  Hoi-Ju Chung ,  Sung-Hoon Kim

    发明人： Seo-Hee Kim ,  Seong-Hyun Jeon ,  Hoi-Ju Chung ,  Sung-Hoon Kim

    IPC分类号： G11C7/00 ,  G11C7/10 ,  G11C7/02

    CPC分类号： G11C7/02 ,  G11C7/1006 ,  G11C13/0004 ,  G11C13/004 ,  G11C13/0061 ,  G11C13/0069 ,  G11C2013/0042 ,  G11C2213/72

    摘要： A nonvolatile memory device is provided, which includes a memory core including a plurality of nonvolatile memory cells, a first read circuit that reads a first codeword from the memory core during a Read While Write (RWW) operation, a second read circuit that reads a second codeword from the memory core during a Read Modification Write (RMW) operation, and a common decoder that is shared by the first read circuit and the second read circuit and selectively decodes the first codeword or the second codeword.

    摘要翻译： 提供了一种非易失性存储器件，其包括包括多个非易失性存储器单元的存储器核心，在读写时（RWW）操作期间从存储器核心读取第一代码字的第一读取电路，读取第一读取电路 在读取修改写入（RMW）操作期间来自存储器核心的第二码字以及由第一读取电路和第二读取电路共享的公共解码器，并且选择性地解码第一码字或第二码字。

    Methods of operating non-volatile memory devices during write operation interruption, non-volatile memory devices, memories and electronic systems operating the same
    7.
    发明授权
    Methods of operating non-volatile memory devices during write operation interruption, non-volatile memory devices, memories and electronic systems operating the same 有权
    在写入操作中断期间操作非易失性存储器件的方法，非易失性存储器件，存储器和操作其的电子系统

    公开(公告)号：US08713408B2

    公开(公告)日：2014-04-29

    申请号：US13193191

    申请日：2011-07-28

    申请人： Kwang Jin Lee ,  Yeong Taek Lee ,  Woo Yeong Cho ,  Hoi Ju Chung

    发明人： Kwang Jin Lee ,  Yeong Taek Lee ,  Woo Yeong Cho ,  Hoi Ju Chung

    IPC分类号： G11C29/00

    CPC分类号： G06F11/1048

    摘要： A non-volatile memory device may operate by writing a portion of a new codeword to an address in the device that stores an old codeword, as part of a write operation. An interruption of the write operation can be detected before completion, which indicates that the address stores the portion of the new codeword and a portion of the old codeword. The portion of the old codeword can be combined with the portion of the new codeword to provide an updated codeword. Error correction bits can be generated using the updated codeword and the error correction bits can be written to the address.

    摘要翻译： 作为写入操作的一部分，非易失性存储器件可以通过将新的码字的一部分写入存储旧码字的设备中的地址来操作。 可以在完成之前检测写入操作的中断，这指示该地址存储新码字的一部分和旧码字的一部分。 旧码字的部分可以与新码字的部分组合以提供更新的码字。 可以使用更新的码字生成纠错位，并且可以将错误校正位写入地址。

    METHODS OF OPERATING NON-VOLATILE MEMORY DEVICES DURING WRITE OPERATION INTERRUPTION, NON-VOLATILE MEMORY DEVICES, MEMORIES AND ELECTRONIC SYSTEMS OPERATING THE SAME
    8.
    发明申请
    METHODS OF OPERATING NON-VOLATILE MEMORY DEVICES DURING WRITE OPERATION INTERRUPTION, NON-VOLATILE MEMORY DEVICES, MEMORIES AND ELECTRONIC SYSTEMS OPERATING THE SAME 有权
    在写操作中断期间操作非易失性存储器件的方法，非易失性存储器件，存储器和操作其的电子系统

    公开(公告)号：US20120311407A1

    公开(公告)日：2012-12-06

    申请号：US13193191

    申请日：2011-07-28

    申请人： Kwang Jin Lee ,  Yeong Taek Lee ,  Woo Yeong Cho ,  Hoi Ju Chung

    发明人： Kwang Jin Lee ,  Yeong Taek Lee ,  Woo Yeong Cho ,  Hoi Ju Chung

    IPC分类号： H03M13/05 ,  G06F11/10

    CPC分类号： G06F11/1048

    摘要： A non-volatile memory device may operate by writing a portion of a new codeword to an address in the device that stores an old codeword, as part of a write operation. An interruption of the write operation can be detected before completion, which indicates that the address stores the portion of the new codeword and a portion of the old codeword. The portion of the old codeword can be combined with the portion of the new codeword to provide an updated codeword. Error correction bits can be generated using the updated codeword and the error correction bits can be written to the address.

    摘要翻译： 作为写入操作的一部分，非易失性存储器件可以通过将新的码字的一部分写入存储旧码字的设备中的地址来操作。 可以在完成之前检测写入操作的中断，这指示该地址存储新码字的一部分和旧码字的一部分。 旧码字的部分可以与新码字的部分组合以提供更新的码字。 可以使用更新的码字生成纠错位，并且可以将错误校正位写入地址。

    Memory Devices Having Controllers that Divide Command Signals Into Two Signals and Systems Including Such Memory Devices
    9.
    发明申请
    Memory Devices Having Controllers that Divide Command Signals Into Two Signals and Systems Including Such Memory Devices 有权
    具有把命令信号分成包含这种存储器件的两个信号和系统的控制器的存储器件

    公开(公告)号：US20120182815A1

    公开(公告)日：2012-07-19

    申请号：US13348672

    申请日：2012-01-12

    申请人： Seong Hyun Jeon ,  Hoi Ju Chung ,  Jung Sunwoo

    发明人： Seong Hyun Jeon ,  Hoi Ju Chung ,  Jung Sunwoo

    IPC分类号： G11C7/00

    CPC分类号： G11C7/1006 ,  G06F11/1048 ,  G06F2213/0038 ,  G11C7/109 ,  G11C7/22 ,  G11C2029/0411

    摘要： A memory device using error correcting code and a system including the same are provided. The memory device includes a memory cell array including a plurality of bit lines and a plurality of memory cells; an access block for accessing the memory cell array; and a controller block for receiving a first operation command signal, dividing the first operation command signal into at least two paths pulse signals corresponding to at least two paths, based on a pre-determined criterion, and then supplying the at least two path pulse signals to the access block. The access block operates based on an output signal of the controller block.

    摘要翻译： 提供了使用纠错码的存储装置和包括该存储装置的系统。 存储器件包括一个包括多个位线和多个存储单元的存储单元阵列; 访问所述存储单元阵列的访问块; 以及控制器块，用于接收第一操作命令信号，基于预定准则将第一操作命令信号划分为与至少两个路径相对应的至少两个路径脉冲信号，然后提供至少两个路径脉冲信号 到访问块。 访问块基于控制器块的输出信号进行操作。

    MEMORY DEVICE USING ERROR CORRECTING CODE AND SYSTEM THEREOF
    10.
    发明申请
    MEMORY DEVICE USING ERROR CORRECTING CODE AND SYSTEM THEREOF 有权
    使用错误修正代码及其系统的存储器件

    公开(公告)号：US20120173956A1

    公开(公告)日：2012-07-05

    申请号：US13339716

    申请日：2011-12-29

    申请人： Seong Hyun Jeon ,  Hoi Ju Chung

    发明人： Seong Hyun Jeon ,  Hoi Ju Chung

    IPC分类号： H03M13/05 ,  G06F11/10

    CPC分类号： H03M13/13 ,  G06F11/1044

    摘要： A memory device using error correcting code and a system including the same are provided. The memory system includes a memory device, and a storage block connected to the memory device. The memory device includes a normal cell region including a first plurality of memory cells for storing data bits, and an error correcting code (ECC) cell region including a second plurality of memory cells for storing first through mth sets of ECC bits. The storage block includes a third plurality of memory cells for storing first through nth sets of the ECC bits. Each memory cell of the first and second plurality of memory cells is a first type of memory cell and each memory cell of the third plurality of memory cells is a second type of memory cell different from the first type of memory cell.

    摘要翻译： 提供了使用纠错码的存储装置和包括该存储装置的系统。 存储器系统包括存储器件和连接到存储器件的存储块。 存储器件包括包括用于存储数据位的第一多个存储单元的正常单元区域和包括用于存储第一至第m组ECC位的第二多个存储器单元的纠错码（ECC）单元区域。 存储块包括用于存储第一至第n组ECC位的第三多个存储单元。 第一和第二多个存储器单元的每个存储器单元是第一类型的存储单元，并且第三多个存储单元的每个存储单元是与第一类型的存储单元不同的第二类型存储单元。