公开(公告)号：US09190120B2

公开(公告)日：2015-11-17

申请号：US13238055

申请日：2011-09-21

申请人： Hojun Shim ,  Woo-Sung Cho

发明人： Hojun Shim ,  Woo-Sung Cho

IPC分类号： G11C5/14

CPC分类号： G11C5/147 ,  G11C16/30

摘要： A data storage device including a reset circuit and a method of resetting thereof includes a memory device to receive a driving voltage through a power terminal thereof, a voltage regulator to adjust an external voltage to provide the adjusted voltage to the power terminal of the memory device, and a reset circuit to discharge an enable terminal of the voltage regulator or the power terminal of the memory device according to a change of the external voltage.

摘要翻译： 包括复位电路的数据存储装置及其复位方法包括：通过其电源端接收驱动电压的存储装置;调节外部电压的电压调节器，用于向存储装置的电源端提供经调整的电压; 以及复位电路，用于根据外部电压的变化对电压调节器的使能端子或存储器件的电源端子进行放电。

公开(公告)号：US08904161B2

公开(公告)日：2014-12-02

申请号：US13239454

申请日：2011-09-22

申请人： Hojun Shim ,  Woo-Sung Cho

发明人： Hojun Shim ,  Woo-Sung Cho

IPC分类号： G06F9/00 ,  G11C5/14 ,  G11C16/22

CPC分类号： G11C16/22 ,  G11C5/143

摘要： Provided is a memory system that includes at least one nonvolatile memory device, a plurality of power lines and a plurality of power domains. The power lines receive a power source voltage. The power domains are respectively connected to the power lines. A reset signal is generated by using voltages which are detected from the power lines. The memory system and a reset method thereof detect the voltages of all power lines to generate a reset signal, and thus enhance reliability of data when a power is shut off.

摘要翻译： 提供了一种包括至少一个非易失性存储器件，多个电源线和多个电源域的存储器系统。 电源线接收电源电压。 电力域分别连接到电力线。 通过使用从电力线检测的电压来产生复位信号。 存储器系统及其复位方法检测所有电力线的电压以产生复位信号，从而在断电时提高数据的可靠性。

公开(公告)号：US08760918B2

公开(公告)日：2014-06-24

申请号：US13137423

申请日：2011-08-15

申请人： Jaesoo Lee ,  Kangho Roh ,  Wonhee Cho ,  Hojun Shim ,  Youngjoon Choi ,  Jaehoon Heo ,  Je-Hyuck Song ,  Seung-Duk Cho ,  Seontaek Kim ,  Moonwook Oh ,  Jong Tae Park ,  Wonmoon Cheon ,  Chanik Park ,  Yang-sup Lee

发明人： Jaesoo Lee ,  Kangho Roh ,  Wonhee Cho ,  Hojun Shim ,  Youngjoon Choi ,  Jaehoon Heo ,  Je-Hyuck Song ,  Seung-Duk Cho ,  Seontaek Kim ,  Moonwook Oh ,  Jong Tae Park ,  Wonmoon Cheon ,  Chanik Park ,  Yang-sup Lee

IPC分类号： G11C16/04

CPC分类号： G11C11/5628 ,  G06F12/0246 ,  G06F2212/7201 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/3418 ,  G11C16/3431 ,  G11C29/00 ,  G11C2211/5621 ,  Y02D10/13

摘要： A memory system is provided with a processor, a main memory, and a flash memory. Performance of the memory system is improved through achievement of speed-up and high data reliability. The memory system includes a nonvolatile memory device and a controller configured to drive a control program to control the nonvolatile memory device. The control program executes a second access operation for the nonvolatile memory device even before a first access operation to the nonvolatile memory device is completed.

公开(公告)号：US08027194B2

公开(公告)日：2011-09-27

申请号：US12457485

申请日：2009-06-12

申请人： Jaesoo Lee ,  Kangho Roh ,  Wonhee Cho ,  Hojun Shim ,  Youngjoon Choi ,  Jaehoon Heo ,  Je-Hyuck Song ,  Seung-Duk Cho ,  Seontaek Kim ,  Moonwook Oh ,  Jong Tae Park ,  Wonmoon Cheon ,  Chanik Park ,  Yang-sup Lee

发明人： Jaesoo Lee ,  Kangho Roh ,  Wonhee Cho ,  Hojun Shim ,  Youngjoon Choi ,  Jaehoon Heo ,  Je-Hyuck Song ,  Seung-Duk Cho ,  Seontaek Kim ,  Moonwook Oh ,  Jong Tae Park ,  Wonmoon Cheon ,  Chanik Park ,  Yang-sup Lee

IPC分类号： G11C16/04

CPC分类号： G11C11/5628 ,  G06F12/0246 ,  G06F2212/7201 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/3418 ,  G11C16/3431 ,  G11C29/00 ,  G11C2211/5621 ,  Y02D10/13

摘要： One embodiment of a nonvolatile memory device includes a memory cell array including a plurality of multi-level cells, and a control unit configured to determine a characteristic of data to be stored in the memory cell array. The control unit is configured to select one of plural multi-bit programming methods based on the determination. Data is stored in the memory cell array according to the selected multi-bit programming method, and at least one of the plural multi-bit programming methods maintains least significant bit data when there is a program fail of most significant bit data.

摘要翻译： 非易失性存储器件的一个实施例包括包括多个多电平单元的存储单元阵列，以及配置为确定要存储在存储单元阵列中的数据的特性的控制单元。 控制单元被配置为基于该确定来选择多个多位编程方法之一。 数据根据所选择的多位编程方法存储在存储单元阵列中，并且当存在最高有效位数据的程序失败时，多个多位编程方法中的至少一个保持最低有效位数据。

公开(公告)号：US20110035536A1

公开(公告)日：2011-02-10

申请号：US12732316

申请日：2010-03-26

申请人： Hojun Shim ,  Je-Hyuck Song

发明人： Hojun Shim ,  Je-Hyuck Song

IPC分类号： G06F12/02 ,  G06F12/00

CPC分类号： G06F12/0246 ,  G06F2212/7211 ,  G11C16/3495

摘要： A non-volatile memory device which includes a non-volatile memory core including a memory cell array and a controller configured to generate wear-leveling information from internal operation information of the memory cell array after a write operation, independent of a request from an external device. The wear-leveling information is selectively provided to the external device.

摘要翻译： 一种非易失性存储器件，其包括包括存储器单元阵列的非易失性存储器核心和被配置为在写入操作之后从存储单元阵列的内部操作信息生成磨损均衡信息的控制器，独立于来自外部的请求 设备。 磨损均衡信息选择性地提供给外部设备。

公开(公告)号：US20090310408A1

公开(公告)日：2009-12-17

申请号：US12457485

申请日：2009-06-12

申请人： Jaesoo Lee ,  Kangho Roh ,  Wonhee Cho ,  Hojun Shim ,  Youngjoon Choi ,  Jaehoon Heo ,  Je-Hyuck Song ,  Seung-Duk Cho ,  Seontaek Kim ,  Moonwook Oh ,  Jong Tae Park ,  Wonmoon Cheon ,  Chanik Park ,  Yang-sup Lee

发明人： Jaesoo Lee ,  Kangho Roh ,  Wonhee Cho ,  Hojun Shim ,  Youngjoon Choi ,  Jaehoon Heo ,  Je-Hyuck Song ,  Seung-Duk Cho ,  Seontaek Kim ,  Moonwook Oh ,  Jong Tae Park ,  Wonmoon Cheon ,  Chanik Park ,  Yang-sup Lee

IPC分类号： G11C16/04 ,  G11C16/06

CPC分类号： G11C11/5628 ,  G06F12/0246 ,  G06F2212/7201 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/3418 ,  G11C16/3431 ,  G11C29/00 ,  G11C2211/5621 ,  Y02D10/13

摘要： A memory system is provided with a processor, a main memory, and a flash memory. Performance of the memory system is improved through achievement of speed-up and high data reliability. The memory system includes a nonvolatile memory device and a controller configured to drive a control program to control the nonvolatile memory device. The control program executes a second access operation for the nonvolatile memory device even before a first access operation to the nonvolatile memory device is completed.

摘要翻译： 存储器系统设置有处理器，主存储器和闪存。 通过实现加速和高数据可靠性，可以提高存储系统的性能。 存储器系统包括非易失性存储器件和被配置为驱动控制程序以控制非易失性存储器件的控制器。 即使在完成对非易失性存储器件的第一访问操作之前，控制程序也执行用于非易失性存储器件的第二访问操作。

公开(公告)号：US08638585B2

公开(公告)日：2014-01-28

申请号：US13137409

申请日：2011-08-12

申请人： Jaesoo Lee ,  Kangho Roh ,  Wonhee Cho ,  Hojun Shim ,  Youngjoon Choi ,  Jaehoon Heo ,  Je-Hyuck Song ,  Seung-Duk Cho ,  Seontaek Kim ,  Moonwook Oh ,  Jong Tae Park ,  Wonmoon Cheon ,  Chanik Park ,  Yang-sup Lee

发明人： Jaesoo Lee ,  Kangho Roh ,  Wonhee Cho ,  Hojun Shim ,  Youngjoon Choi ,  Jaehoon Heo ,  Je-Hyuck Song ,  Seung-Duk Cho ,  Seontaek Kim ,  Moonwook Oh ,  Jong Tae Park ,  Wonmoon Cheon ,  Chanik Park ,  Yang-sup Lee

IPC分类号： G11C5/02

CPC分类号： G11C11/5628 ,  G06F12/0246 ,  G06F2212/7201 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/3418 ,  G11C16/3431 ,  G11C29/00 ,  G11C2211/5621 ,  Y02D10/13

摘要： A memory system is provided with a processor, a main memory, and a flash memory. Performance of the memory system is improved through achievement of speed-up and high data reliability. The memory system includes a nonvolatile memory device and a controller configured to drive a control program to control the nonvolatile memory device. The control program executes a second access operation for the nonvolatile memory device even before a first access operation to the nonvolatile memory device is completed.

公开(公告)号：US08565021B2

公开(公告)日：2013-10-22

申请号：US13137401

申请日：2011-08-11

申请人： Jaesoo Lee ,  Kangho Roh ,  Wonhee Cho ,  Hojun Shim ,  Youngjoon Choi ,  Jaehoon Heo ,  Je-Hyuck Song ,  Seung-Duk Cho ,  Seontaek Kim ,  Moonwook Oh ,  Jong Tae Park ,  Wonmoon Cheon ,  Chanik Park ,  Yang-sup Lee

发明人： Jaesoo Lee ,  Kangho Roh ,  Wonhee Cho ,  Hojun Shim ,  Youngjoon Choi ,  Jaehoon Heo ,  Je-Hyuck Song ,  Seung-Duk Cho ,  Seontaek Kim ,  Moonwook Oh ,  Jong Tae Park ,  Wonmoon Cheon ,  Chanik Park ,  Yang-sup Lee

IPC分类号： G11C16/04

CPC分类号： G11C11/5628 ,  G06F12/0246 ,  G06F2212/7201 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/3418 ,  G11C16/3431 ,  G11C29/00 ,  G11C2211/5621 ,  Y02D10/13

摘要： A memory system is provided with a processor, a main memory, and a flash memory. Performance of the memory system is improved through achievement of speed-up and high data reliability. The memory system includes a nonvolatile memory device and a controller configured to drive a control program to control the nonvolatile memory device. The control program executes a second access operation for the nonvolatile memory device even before a first access operation to the nonvolatile memory device is completed.

公开(公告)号：US20110299335A1

公开(公告)日：2011-12-08

申请号：US13137401

申请日：2011-08-11

申请人： Jaesoo Lee ,  Kangho Roh ,  Wonhee Cho ,  Hojun Shim ,  Youngjoon Choi ,  Jaehoon Heo ,  Je-Hyuck Song ,  Seung-Duk Cho ,  Seontaek Kim ,  Moonwook Oh ,  Jong Tae Park ,  Wonmoon Cheon ,  Chanik Park ,  Yang-sup Lee

发明人： Jaesoo Lee ,  Kangho Roh ,  Wonhee Cho ,  Hojun Shim ,  Youngjoon Choi ,  Jaehoon Heo ,  Je-Hyuck Song ,  Seung-Duk Cho ,  Seontaek Kim ,  Moonwook Oh ,  Jong Tae Park ,  Wonmoon Cheon ,  Chanik Park ,  Yang-sup Lee

IPC分类号： G11C16/10

CPC分类号： G11C11/5628 ,  G06F12/0246 ,  G06F2212/7201 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/3418 ,  G11C16/3431 ,  G11C29/00 ,  G11C2211/5621 ,  Y02D10/13

摘要： A memory system is provided with a processor, a main memory, and a flash memory. Performance of the memory system is improved through achievement of speed-up and high data reliability. The memory system includes a nonvolatile memory device and a controller configured to drive a control program to control the nonvolatile memory device. The control program executes a second access operation for the nonvolatile memory device even before a first access operation to the nonvolatile memory device is completed.

公开(公告)号：US20100217966A1

公开(公告)日：2010-08-26

申请号：US12656715

申请日：2010-02-16

申请人： Hojun Shim

发明人： Hojun Shim

IPC分类号： G06F9/00 ,  G06F13/36 ,  G06F12/16

CPC分类号： G06F9/4401

摘要： The booting method of a computing system includes determining whether boot data of an operating system is pinned to a main memory, reading boot data from a storage device to pin the read boot data to the main memory when relocation of the pinned boot data is required, and performing a booting operation using the pinned boot data.

摘要翻译： 计算系统的启动方法包括：确定操作系统的启动数据是否被固定到主存储器，当需要重新定位被固定的引导数据时，从存储设备读取引导数据以将读引导数据引导到主存储器， 并使用固定引导数据执行引导操作。