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1.发明授权Method and apparatus for identifying plug-to-plug short from a charged particle microscopic image 有权用于从带电粒子显微镜图像识别插头插头的方法和装置公开(公告)号：US08759762B2
公开(公告)日：2014-06-24
申请号：US12483220
申请日：2009-06-11
IPC分类号： H01J37/26 , H01J37/28 , H01J37/147
CPC分类号： H01J37/26 , H01J37/1474 , H01J37/263 , H01J37/28 , H01L22/12
摘要： A method of inspecting for plug-to-plug short (short circuit) defects on a sample is disclosed. A charged particle beam for imaging the sample is repeatedly line-scanned over the sample with a line-to-line advancement direction perpendicular to the line-scan direction. The method includes scanning the sample with a line-to-line advancement along a first and a second direction, to obtain a first and a second image of the sample, respectively. Then, the method includes identifying plug patterns, represented in the obtained images with abnormal grey levels, as abnormal plug patterns. Next, the method compares the locations of the abnormal plug patterns to determine the presence of plug-to-plug short defects on the sample.
摘要翻译： 公开了一种检查样品上插头短插（短路）缺陷的方法。 用于对样品进行成像的带电粒子束在垂直于线扫描方向的线对线前进方向上在样品上重复线扫描。 该方法包括沿着第一和第二方向以线对线前进扫描样品，以分别获得样品的第一和第二图像。 然后，该方法包括将获得的具有异常灰度级的图像表示的插头图案识别为异常插头图案。 接下来，该方法比较异常插头图案的位置，以确定样品上插头到插头短缺陷的存在。
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公开(公告)号：US20080215276A1
公开(公告)日：2008-09-04
申请号：US11951173
申请日：2007-12-05
申请人： Wei Fang , Jack Y. Jau , Hong Xiao
发明人： Wei Fang , Jack Y. Jau , Hong Xiao
IPC分类号： G06F19/00
CPC分类号： G03F7/70283 , G03F1/00 , G03F7/70633 , H01L22/20
摘要： A method and system for controlling an overlay shift on an integrated circuit is disclosed. The method and system comprises utilizing a scanning electron microscope (SEM) to measure the overlay shift between a first mask and a second mask of the circuit after a second mask and comparing the overlay shift to information about the integrated circuit in a database. The method and system includes providing a control mechanism to analyze the overlay shift and feed forward to the fabrication process before a third mask for error correction.A system and method in accordance with the present invention advantageously utilizes a scanning electron microscope (SEM) image overlay measurement after the fabrication process such as etching and chemical mechanical polishing (CMP).
摘要翻译： 公开了一种用于控制集成电路上的覆盖移位的方法和系统。 该方法和系统包括利用扫描电子显微镜（SEM）在第二掩模之后测量电路的第一掩模和第二掩模之间的覆盖位移，并将覆盖位移与数据库中的集成电路的信息进行比较。 该方法和系统包括提供控制机构以分析覆盖位移并在用于纠错的第三掩模之前向前馈到制造过程。 根据本发明的系统和方法有利地在诸如蚀刻和化学机械抛光（CMP）的制造工艺之后利用扫描电子显微镜（SEM）图像覆盖测量。
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3.发明申请Method for Inspecting Overlay Shift Defect during Semiconductor Manufacturing and Apparatus Thereof 有权半导体制造过程中检查覆盖偏移缺陷的方法及其设备公开(公告)号：US20100278416A1
公开(公告)日：2010-11-04
申请号：US12433762
申请日：2009-04-30
CPC分类号： H01L21/67242 , G03F7/70633
摘要： A method of inspecting for overlay shift defects during semiconductor manufacturing is disclosed. The method can include the steps of providing a charged particle microscopic image of a sample, identifying an inspection pattern period in the charged particle microscopic image, averaging the charged particle microscopic image by using the inspection pattern period to form an averaged inspection pattern period, estimating an average width from the averaged inspection pattern period, and comparing the average width with a predefined threshold value to determine the presence of an overlay shift defect.
摘要翻译： 公开了一种在半导体制造期间检查覆盖偏移缺陷的方法。 该方法可以包括以下步骤：提供样品的带电粒子显微镜图像，识别带电粒子显微镜图像中的检查图案周期，通过使用检查图案周期平均化带电粒子显微镜图像以形成平均检查图案周期，估计 从平均检查图案周期的平均宽度，以及将平均宽度与预定义的阈值进行比较，以确定覆盖位移缺陷的存在。
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4.发明授权Method for inspecting overlay shift defect during semiconductor manufacturing and apparatus thereof 有权在半导体制造期间检查重叠移位缺陷的方法及其装置公开(公告)号：US08923601B2
公开(公告)日：2014-12-30
申请号：US13240721
申请日：2011-09-22
CPC分类号： G03F7/70633
摘要： A method for inspecting overlay shift defect during semiconductor manufacturing is disclosed herein and includes a step for providing a charged particle microscopic image of a sample, a step for identifying an inspection pattern measure in the charged particle microscopic image, a step for averaging the charged particle microscopic image by using the inspection pattern measure to form an averaged inspection pattern measure, a step for estimating an average width from the averaged inspection pattern measure, and a step for comparing the average width with a predefined threshold value to determine the presence of the overlay shift defect.
摘要翻译： 本文公开了一种用于在半导体制造期间检查覆盖偏移缺陷的方法，并且包括用于提供样品的带电粒子显微镜图像的步骤，用于识别带电粒子显微镜图像中的检查图案测量的步骤，用于使带电粒子平均的步骤 通过使用检查图案测量形成平均检查图案测量的微观图像，从平均检查图案度量估计平均宽度的步骤，以及将平均宽度与预定阈值进行比较以确定覆盖层的存在的步骤 移位缺陷。
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公开(公告)号：US08432441B2
公开(公告)日：2013-04-30
申请号：US13032105
申请日：2011-02-22
IPC分类号： H04N7/18
CPC分类号： H04N7/18 , G06T7/0004 , G06T7/001 , G06T2207/10061 , G06T2207/20016 , G06T2207/30148 , H04N7/183
摘要： A method for measuring critical dimension (CD) includes steps of: scanning at least one area of interest of a die to obtain at least one scanned image; aligning the scanned image to at least one designed layout pattern to identify a plurality of borders within the scanned image; and averaging distances each measured from the border or the plurality of borders of a pattern associated with a specific type of CD corresponding to the designed layout pattern to obtain a value of CD of the die. The value of critical dimensions of dies can be obtained from the scanned image with lower resolution which is obtained by relatively higher scanning speed, so the above-mentioned method can obtain value of CD for every die within entire wafer to monitor the uniformity of the semiconductor manufacturing process within an acceptable inspection time.
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6.发明授权Method for inspecting overlay shift defect during semiconductor manufacturing and apparatus thereof 有权在半导体制造期间检查重叠移位缺陷的方法及其装置公开(公告)号：US08050490B2
公开(公告)日：2011-11-01
申请号：US12433762
申请日：2009-04-30
IPC分类号： G06K9/00
CPC分类号： H01L21/67242 , G03F7/70633
摘要： A method of inspecting for overlay shift defects during semiconductor manufacturing is disclosed. The method can include the steps of providing a charged particle microscopic image of a sample, identifying an inspection pattern period in the charged particle microscopic image, averaging the charged particle microscopic image by using the inspection pattern period to form an averaged inspection pattern period, estimating an average width from the averaged inspection pattern period, and comparing the average width with a predefined threshold value to determine the presence of an overlay shift defect.
摘要翻译： 公开了一种在半导体制造期间检查覆盖偏移缺陷的方法。 该方法可以包括以下步骤：提供样品的带电粒子显微镜图像，识别带电粒子显微镜图像中的检查图案周期，通过使用检查图案周期平均化带电粒子显微镜图像以形成平均检查图案周期，估计 从平均检查图案周期的平均宽度，以及将平均宽度与预定义的阈值进行比较，以确定覆盖位移缺陷的存在。
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公开(公告)号：US08010307B2
公开(公告)日：2011-08-30
申请号：US11951173
申请日：2007-12-05
申请人： Wei Fang , Jack Y. Jau , Hong Xiao
发明人： Wei Fang , Jack Y. Jau , Hong Xiao
IPC分类号： G06F19/00
CPC分类号： G03F7/70283 , G03F1/00 , G03F7/70633 , H01L22/20
摘要： A method and system for controlling an overlay shift on an integrated circuit is disclosed. The method and system comprises utilizing a scanning electron microscope (SEM) to measure the overlay shift between a first mask and a second mask of the circuit after a second mask and comparing the overlay shift to information about the integrated circuit in a database. The method and system includes providing a control mechanism to analyze the overlay shift and feed forward to the fabrication process before a third mask for error correction. A system and method in accordance with the present invention advantageously utilizes a scanning electron microscope (SEM) image overlay measurement after the fabrication process such as etching and chemical mechanical polishing (CMP).
摘要翻译： 公开了一种用于控制集成电路上的覆盖移位的方法和系统。 该方法和系统包括利用扫描电子显微镜（SEM）在第二掩模之后测量电路的第一掩模和第二掩模之间的覆盖位移，并将覆盖位移与数据库中的集成电路的信息进行比较。 该方法和系统包括提供控制机构以分析覆盖位移并在用于纠错的第三掩模之前向前馈到制造过程。 根据本发明的系统和方法有利地在诸如蚀刻和化学机械抛光（CMP）的制造工艺之后利用扫描电子显微镜（SEM）图像覆盖测量。
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8.发明授权Structure and method for determining a defect in integrated circuit manufacturing process 有权用于确定集成电路制造过程中的缺陷的结构和方法公开(公告)号：US09035674B2
公开(公告)日：2015-05-19
申请号：US13323634
申请日：2011-12-12
申请人： Hong Xiao , Jack Y. Jau , Chang Chun Yeh
发明人： Hong Xiao , Jack Y. Jau , Chang Chun Yeh
IPC分类号： H01L21/66
摘要： The present invention discloses a structure and method for determining a defect in integrated circuit manufacturing process, wherein the structure comprises a plurality of normal active areas formed in a plurality of first arrays and a plurality of defective active areas formed in a plurality of second arrays. The first arrays and second arrays are interlaced, and the defect is determined by monitoring a voltage contrast from a charged particle microscope image of the active areas.
摘要翻译： 本发明公开了一种用于确定集成电路制造过程中的缺陷的结构和方法，其中该结构包括形成在多个第一阵列中的多个正常有源区和形成在多个第二阵列中的多个有缺陷的有源区。 第一阵列和第二阵列是交错的，并且通过监视来自有源区域的带电粒子显微镜图像的电压对比来确定缺陷。
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9.发明授权Method and system for heating substrate in vacuum environment and method and system for identifying defects on substrate 有权在真空环境中加热基材的方法和系统以及用于识别基材上的缺陷的方法和系统公开(公告)号：US08809779B2
公开(公告)日：2014-08-19
申请号：US12339558
申请日：2008-12-19
申请人： Hong Xiao , Yi-Xiang Wang
发明人： Hong Xiao , Yi-Xiang Wang
CPC分类号： H05B3/0047 , G01N23/2202
摘要： A method for heating a substrate in a vacuum environment and a system therefor is provided. The system includes a chamber capable of holding the substrate located in the vacuum environment and a light source capable of projecting a light beam only on a portion of the substrate. The method includes the following steps. First, the substrate is placed in the vacuumed chamber. Thereafter, the light beam emitted from the light source is projected on the portion of the substrate, such that the portion is significantly heated before whole the substrate is heated. When the light beam is a charged particle beam projected by a charged particle beam assembly and projected on defects located on the substrate, the defects are capable of being identified by an examination result provided by an examination assembly after termination of light beam projection.
摘要翻译： 提供一种在真空环境中加热基板的方法及其系统。 该系统包括能够保持位于真空环境中的衬底的腔室和能够仅将光束投射到衬底的一部分上的光源。 该方法包括以下步骤。 首先，将基板放置在真空室中。 此后，从光源发射的光束被投射在基板的部分上，使得该部分在整个基板被加热之前被显着地加热。 当光束是由带电粒子束组件投射并投影在基板上的缺陷上的带电粒子束时，能够通过在光束投影终止之后由检查组件提供的检查结果来识别缺陷。
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10.发明授权Structure and method for determining a defect in integrated circuit manufacturing process 有权用于确定集成电路制造过程中的缺陷的结构和方法公开(公告)号：US08754372B2
公开(公告)日：2014-06-17
申请号：US13312152
申请日：2011-12-06
申请人： Hong Xiao
发明人： Hong Xiao
IPC分类号： H01J37/26
CPC分类号： H01J37/26 , G01R31/024 , G01R31/307 , G11C11/401 , G11C2029/0403 , H01J2237/24592 , H01J2237/2594 , H01J2237/2814 , H01L22/12
摘要： The present invention discloses a structure and a method for determining a defect in integrated circuit manufacturing process. Test keys are designed for the structure to be the interlaced arrays of grounded and floating conductive cylinders, and the microscopic image can be predicted to be an interlaced pattern of bright voltage contrast (BVC) and dark voltage contrast (DVC) signals for a charged particle beam imaging system. The system can detect the defects by comparing patterns of the detected VC signals and the predicted VC signals.
摘要翻译： 本发明公开了一种用于确定集成电路制造工艺中的缺陷的结构和方法。 测试键设计用于结构为接地和浮动导电圆柱体的隔行阵列，并且微观图像可以预测为带电粒子的亮电压对比度（BVC）和暗电压对比度（DVC）信号的隔行扫描模式 光束成像系统。 该系统可以通过比较检测到的VC信号和预测的VC信号的模式来检测缺陷。
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