公开(公告)号：US20140015068A1

公开(公告)日：2014-01-16

申请号：US13699731

申请日：2012-07-24

申请人： Hong Yang ,  Wenwu Wang ,  Huaxiang Yin ,  Jiang Yan ,  Xueli Ma

发明人： Hong Yang ,  Wenwu Wang ,  Huaxiang Yin ,  Jiang Yan ,  Xueli Ma

IPC分类号： H01L29/49 ,  H01L21/28

CPC分类号： H01L29/495 ,  H01L21/28008 ,  H01L21/28088 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517

摘要： The disclosure relates to a gate structure, a semiconductor device and methods for forming the same. An embodiment of the disclosure provides a method for forming a gate structure, including: providing a substrate; forming an interface layer on the substrate; forming a gate dielectric layer on the interface layer; forming a gate dielectric capping layer on the gate dielectric layer; forming an etching stop layer on the gate dielectric capping layer; forming an oxygen scavenging element layer on the etching stop layer; forming an oxygen scavenging element capping layer on the oxygen scavenging element layer; performing Post-Metallization Annealing; performing etching until the etching stop layer is exposed; forming a work function adjustment layer on the etching stop layer; and forming a gate layer on the work function adjustment layer.

摘要翻译： 本公开涉及一种栅极结构，半导体器件及其形成方法。 本公开的实施例提供了一种用于形成栅极结构的方法，包括：提供基板; 在衬底上形成界面层; 在界面层上形成栅介电层; 在所述栅极电介质层上形成栅介电覆盖层; 在所述栅极电介质覆盖层上形成蚀刻停止层; 在所述蚀刻停止层上形成氧清除元件层; 在除氧元件层上形成氧清除元件盖层; 执行金属后退火; 进行蚀刻，直到蚀刻停止层露出为止; 在所述蚀刻停止层上形成功函数调整层; 以及在所述功函数调整层上形成栅极层。

公开(公告)号：US20140015063A1

公开(公告)日：2014-01-16

申请号：US13699734

申请日：2012-07-24

申请人： Hong Yang ,  Xueli Ma ,  Wenwu Wang ,  Kai Han ,  Xiaolei Wang ,  Huaxiang Yin ,  Jiang Yan

发明人： Hong Yang ,  Xueli Ma ,  Wenwu Wang ,  Kai Han ,  Xiaolei Wang ,  Huaxiang Yin ,  Jiang Yan

IPC分类号： H01L21/8238 ,  H01L27/092

CPC分类号： H01L21/8238 ,  H01L21/823842 ,  H01L21/823857 ,  H01L27/092

摘要： A method for forming a gate structure, comprising: providing a substrate, where the substrate includes a nMOSFET area and a pMOSFET area, each of the nMOSFET area and the pMOSFET area has a gate trench, and each of the gate trenches is provided at a bottom portion with a gate dielectric layer; forming a gate dielectric capping layer on the substrate; forming an etching stop layer on the gate dielectric capping layer; forming an oxygen scavenging element layer on the etching stop layer; forming a first work function adjustment layer on the oxygen scavenging element layer; etching the first work function adjustment layer above the nMOSFET area; forming a second work function adjustment layer on the surface of the substrate; metal layer depositing and annealing to fill the gate trenches with a metal layer; and removing the metal layer outside the gate trenches.

摘要翻译： 一种用于形成栅极结构的方法，包括：提供衬底，其中所述衬底包括nMOSFET区域和pMOSFET区域，nMOSFET区域和pMOSFET区域中的每一个具有栅极沟槽，并且每个栅极沟槽设置在 底部具有栅极电介质层; 在所述衬底上形成栅介电覆盖层; 在所述栅极电介质覆盖层上形成蚀刻停止层; 在所述蚀刻停止层上形成氧清除元件层; 在除氧元件层上形成第一功函数调整层; 蚀刻nMOSFET区域上方的第一功函数调整层; 在所述基板的表面上形成第二功函数调整层; 金属层沉积和退火以用金属层填充栅极沟槽; 以及去除栅极沟槽外的金属层。

公开(公告)号：US20140015062A1

公开(公告)日：2014-01-16

申请号：US13699732

申请日：2012-07-24

申请人： Hong Yang ,  Xueli Ma ,  Wenwu Wang ,  Kai Han ,  Xiaolei Wang ,  Huaxiang Yin ,  Jiang Yan

发明人： Hong Yang ,  Xueli Ma ,  Wenwu Wang ,  Kai Han ,  Xiaolei Wang ,  Huaxiang Yin ,  Jiang Yan

IPC分类号： H01L21/8238 ,  H01L27/092

CPC分类号： H01L21/823857 ,  H01L21/823842 ,  H01L27/092

摘要： An embodiment of the present disclosure provides a method for forming a gate structure, comprising: providing a substrate, where the substrate includes a nMOSFET area and a pMOSFET area, each of the nMOSFET area and the pMOSFET area has a gate trench, and each of the gate trenches is provided at a bottom portion with a gate dielectric layer; forming a gate dielectric capping layer on a surface of the substrate; forming an oxygen scavenging element layer on the gate dielectric capping layer; forming an etching stop layer on the oxygen scavenging element layer; forming a work function adjustment layer on the etching stop layer; performing metal layer deposition and annealing process to fill the gate trenches with a metal layer; and removing the metal layer outside the gate trenches.

摘要翻译： 本公开的实施例提供了一种用于形成栅极结构的方法，包括：提供衬底，其中衬底包括nMOSFET区域和pMOSFET区域，nMOSFET区域和pMOSFET区域中的每一个具有栅极沟槽，并且 栅极沟槽在底部设置有栅极电介质层; 在所述衬底的表面上形成栅介电覆盖层; 在所述栅介质顶盖层上形成氧清除元件层; 在除氧元件层上形成蚀刻停止层; 在所述蚀刻停止层上形成功函数调整层; 执行金属层沉积和退火工艺以用金属层填充栅极沟槽; 以及去除栅极沟槽外的金属层。

公开(公告)号：US08921171B2

公开(公告)日：2014-12-30

申请号：US13699734

申请日：2012-07-24

申请人： Hong Yang ,  Xueli Ma ,  Wenwu Wang ,  Kai Han ,  Xiaolei Wang ,  Huaxiang Yin ,  Jiang Yan

发明人： Hong Yang ,  Xueli Ma ,  Wenwu Wang ,  Kai Han ,  Xiaolei Wang ,  Huaxiang Yin ,  Jiang Yan

IPC分类号： H01L21/8238 ,  H01L27/092

CPC分类号： H01L21/8238 ,  H01L21/823842 ,  H01L21/823857 ,  H01L27/092

摘要： A method for forming a gate structure, comprising: providing a substrate, where the substrate includes a nMOSFET area and a pMOSFET area, each of the nMOSFET area and the pMOSFET area has a gate trench, and each of the gate trenches is provided at a bottom portion with a gate dielectric layer; forming a gate dielectric capping layer on the substrate; forming an etching stop layer on the gate dielectric capping layer; forming an oxygen scavenging element layer on the etching stop layer; forming a first work function adjustment layer on the oxygen scavenging element layer; etching the first work function adjustment layer above the nMOSFET area; forming a second work function adjustment layer on the surface of the substrate; metal layer depositing and annealing to fill the gate trenches with a metal layer; and removing the metal layer outside the gate trenches.

摘要翻译： 一种用于形成栅极结构的方法，包括：提供衬底，其中所述衬底包括nMOSFET区域和pMOSFET区域，nMOSFET区域和pMOSFET区域中的每一个具有栅极沟槽，并且每个栅极沟槽设置在 底部具有栅极电介质层; 在所述衬底上形成栅介电覆盖层; 在所述栅极电介质覆盖层上形成蚀刻停止层; 在所述蚀刻停止层上形成氧清除元件层; 在除氧元件层上形成第一功函数调整层; 蚀刻nMOSFET区域上方的第一功函数调整层; 在所述基板的表面上形成第二功函数调整层; 金属层沉积和退火以用金属层填充栅极沟槽; 以及去除栅极沟槽外的金属层。

公开(公告)号：US20120021584A1

公开(公告)日：2012-01-26

申请号：US13061655

申请日：2010-09-28

申请人： Wenwu Wang ,  Xueli Ma ,  Wen Ou ,  Dapeng Chen

发明人： Wenwu Wang ,  Xueli Ma ,  Wen Ou ,  Dapeng Chen

IPC分类号： H01L21/336

CPC分类号： H01L29/0847 ,  H01L29/165 ,  H01L29/66636 ,  H01L29/7834 ,  H01L29/7848

摘要： The present invention provides a semiconductor device and a method for manufacturing the same. The method includes: providing a substrate; forming a gate stack on the substrate; forming an inter layer dielectric (ILD) to cover the device; etching the ILD at both sides of the gate stack and the substrate below the ILD, so as to form a groove of source and drain regions respectively; depositing a metal diffusion barrier layer in the groove; and filling the groove with a metal to form the source and drain regions. The semiconductor device includes: a substrate; a gate stack on the substrate; an inter layer dielectric (ILD) covering the device; a groove of source and drain regions formed in the ILD at both sides of the gate stack and the substrate below the ILD; and a metal diffusion barrier layer and a metal filler formed in the groove. According to the present invention, the S/D parasitic resistance in the MOS device is reduced, the S/D stress on the channel is increased, the process temperature is lowered, and the process compatibility between the high k gate dielectric layer and the metal gate is improved.

摘要翻译： 本发明提供一种半导体器件及其制造方法。 该方法包括：提供衬底; 在基板上形成栅叠层; 形成层间电介质（ILD）以覆盖该器件; 在栅极堆叠的两侧和ILD下面的衬底上蚀刻ILD，以分别形成源极和漏极区的沟槽; 在槽内沉积金属扩散阻挡层; 并用金属填充凹槽以形成源区和漏区。 半导体器件包括：衬底; 衬底上的栅极堆叠; 覆盖该器件的层间电介质（ILD）; 源极和漏极区域的沟槽，形成在栅极堆叠的两侧的ILD和ILD下面的衬底; 以及形成在所述槽中的金属扩散阻挡层和金属填料。 根据本发明，MOS器件中的S / D寄生电阻降低，沟道上的S / D应力增加，处理温度降低，并且高k栅介质层与金属之间的工艺相容性 门改善。

公开(公告)号：US08415222B2

公开(公告)日：2013-04-09

申请号：US13061655

申请日：2010-09-28

申请人： Wenwu Wang ,  Xueli Ma ,  Wen Ou ,  Dapeng Chen

发明人： Wenwu Wang ,  Xueli Ma ,  Wen Ou ,  Dapeng Chen

IPC分类号： H01L21/336

CPC分类号： H01L29/0847 ,  H01L29/165 ,  H01L29/66636 ,  H01L29/7834 ,  H01L29/7848

摘要： The present invention provides a semiconductor device and a method for manufacturing the same. The method includes: providing a substrate; forming a gate stack on the substrate; forming an inter layer dielectric (ILD) to cover the device; etching the ILD at both sides of the gate stack and the substrate below the ILD, so as to form a groove of source and drain regions respectively; depositing a metal diffusion barrier layer in the groove; and filling the groove with a metal to form the source and drain regions. The semiconductor device includes: a substrate; a gate stack on the substrate; an inter layer dielectric (ILD) covering the device; a groove of source and drain regions formed in the ILD at both sides of the gate stack and the substrate below the ILD; and a metal diffusion barrier layer and a metal filler formed in the groove. According to the present invention, the S/D parasitic resistance in the MOS device is reduced, the S/D stress on the channel is increased, the process temperature is lowered, and the process compatibility between the high k gate dielectric layer and the metal gate is improved.

摘要翻译： 本发明提供一种半导体器件及其制造方法。 该方法包括：提供衬底; 在基板上形成栅叠层; 形成层间电介质（ILD）以覆盖该器件; 在栅极堆叠的两侧和ILD下面的衬底上蚀刻ILD，以分别形成源极和漏极区的沟槽; 在槽内沉积金属扩散阻挡层; 并用金属填充凹槽以形成源区和漏区。 半导体器件包括：衬底; 衬底上的栅极堆叠; 覆盖该器件的层间电介质（ILD）; 源极和漏极区域的沟槽，形成在栅极堆叠的两侧的ILD和ILD下面的衬底; 以及形成在所述槽中的金属扩散阻挡层和金属填料。 根据本发明，MOS器件中的S / D寄生电阻降低，沟道上的S / D应力增加，处理温度降低，并且高k栅介质层与金属之间的工艺相容性 门改善。

公开(公告)号：US08410541B2

公开(公告)日：2013-04-02

申请号：US12935364

申请日：2010-06-24

申请人： Wenwu Wang ,  Huilong Zhu ,  Shijie Chen ,  Dapeng Chen

发明人： Wenwu Wang ,  Huilong Zhu ,  Shijie Chen ,  Dapeng Chen

IPC分类号： H01L29/792

CPC分类号： H01L29/513 ,  H01L21/823842 ,  H01L21/823857 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/6659 ,  H01L29/7833

摘要： There is provided a CMOSFET device with threshold voltage controlled by means of interface dipoles and a method of fabricating the same. A cap layer, for example a very thin layer of poly-silicon, amorphous silicon, or SiO2, is interposed inside high-k gate dielectric layers of the CMOSFET device, and the threshold voltage is adjusted by means of the interface dipoles formed by the cap layer inside the high-k gate dielectric layers. According to the present invention, it is possible to effectively optimize the threshold voltage of the CMOSFET device without significantly increasing EOT thereof.

摘要翻译： 提供了具有通过接口偶极子控制的阈值电压的CMOSFET器件及其制造方法。 覆盖层，例如非常薄的多晶硅，非晶硅或SiO 2层被插入在CMOSFET器件的高k栅极电介质层的内部，并且阈值电压通过由 盖层在高k栅介质层内。 根据本发明，可以有效地优化CMOSFET器件的阈值电压而不显着增加其EOT。

公开(公告)号：US20120146223A1

公开(公告)日：2012-06-14

申请号：US13139063

申请日：2011-01-27

申请人： Chao Zhao ,  Wenwu Wang

发明人： Chao Zhao ,  Wenwu Wang

IPC分类号： H01L21/28 ,  H01L23/48

CPC分类号： H01L27/101 ,  H01L21/76814 ,  H01L21/76831 ,  H01L21/76843 ,  H01L21/76849 ,  H01L21/76855 ,  H01L21/76864 ,  H01L21/76873 ,  H01L23/53238 ,  H01L27/2436 ,  H01L29/78 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/1633 ,  H01L2924/0002 ,  H01L2924/00

摘要： A manufacturing method of a MOS device with memory function is provided, which includes: providing a semiconductor substrate, a surface of the semiconductor substrate being covered by a first dielectric layer, a metal interconnect structure being formed in the first dielectric layer; forming a second dielectric layer overlying a surface of the first dielectric layer and the metal interconnect structure; forming an opening in the second dielectric layer, a bottom of the opening revealing the metal interconnect structure; forming an alloy layer at the bottom of the opening, material of the alloy layer containing copper and other metal; and performing a thermal treatment to the alloy layer and the metal interconnect structure to form, on the surface of the metal interconnect structure, a compound layer containing oxygen element. The compound layer containing oxygen element and the MOS device formed in the semiconductor substrate constitute a MOS device with memory function. The method provides a processing which has high controllability and improves the performance of devices.

摘要翻译： 提供具有记忆功能的MOS器件的制造方法，其包括：提供半导体衬底，半导体衬底的表面被第一介电层覆盖，金属互连结构形成在第一介电层中; 形成覆盖在所述第一电介质层和所述金属互连结构的表面上的第二电介质层; 在所述第二介电层中形成开口，所述开口的底部露出所述金属互连结构; 在开口的底部形成合金层，含有铜等金属的合金层的材料; 对合金层和金属互连结构进行热处理，在金属互连结构的表面形成含有氧元素的化合物层。 包含氧元素的化合物层和形成在半导体衬底中的MOS器件构成具有记忆功能的MOS器件。 该方法提供了具有高可控性和提高设备性能的处理。

公开(公告)号：US20120043592A1

公开(公告)日：2012-02-23

申请号：US13132985

申请日：2011-02-23

申请人： Chao Zhao ,  Wenwu Wang ,  Huilong Zhu

发明人： Chao Zhao ,  Wenwu Wang ,  Huilong Zhu

IPC分类号： H01L29/772 ,  H01L21/768

CPC分类号： H01L23/485 ,  H01L21/76847 ,  H01L23/53238 ,  H01L23/53252 ,  H01L23/53266 ,  H01L29/78 ,  H01L2924/0002 ,  H01L2924/00

摘要： The present invention provides a semiconductor device. The semiconductor device comprises contact plugs that comprise a first contact plug formed by a first barrier layer arranged on the source and drain regions and a tungsten layer arranged on the first barrier layer; and second contact plugs comprising a second barrier layer arranged on both of the metal gate and the first contact plug and a conductive layer arranged on the second barrier layer. The conductivity of the conductive layer is higher than that of the tungsten layer. A method for forming the semiconductor device is also provided. The present invention provides the advantage of enhancing the reliability of the device when using the copper contact technique.

摘要翻译： 本发明提供一种半导体器件。 半导体器件包括接触插塞，其包括由布置在源区和漏区上的第一阻挡层和布置在第一阻挡层上的钨层形成的第一接触插塞; 以及第二接触插塞，其包括布置在金属栅极和第一接触插塞两者上的第二阻挡层和布置在第二阻挡层上的导电层。 导电层的导电性高于钨层。 还提供了一种用于形成半导体器件的方法。 本发明提供了当使用铜接触技术时提高器件的可靠性的优点。

公开(公告)号：US20110169097A1

公开(公告)日：2011-07-14

申请号：US12937444

申请日：2010-06-24

申请人： Wenwu Wang ,  Huilong Zhu ,  Shijie Chen ,  Dapeng Chen

发明人： Wenwu Wang ,  Huilong Zhu ,  Shijie Chen ,  Dapeng Chen

IPC分类号： H01L27/092 ,  H01L21/28

CPC分类号： H01L21/823857 ,  H01L27/092 ,  H01L29/513 ,  H01L29/517 ,  H01L29/6659 ,  H01L29/7833

摘要： There is provided a CMOSFET device with a threshold voltage controlled by means of its gate stack configuration and a method of fabricating the same. The CMOSFET device comprises: a semiconductor substrate; an interface layer grown on the silicon substrate; a first high-k gate dielectric layer deposited on the interface layer; a very thin metal layer deposited on the first high-k gate dielectric layer; a second high-k gate dielectric layer deposited on the metal layer; and a gate electrode layer deposited on the second high-k gate dielectric layer. According to to the present invention, the very thin metal layers are deposited between the high-k gate dielectric layers for NMOS and PMOS devices respectively, such that a flat band voltage of the device is adjusted by means of positive or negative charges generated by the metal layers inside the high-k gate dielectric layers, and thus the threshold voltage of the device is controlled. Thus, it is possible not only to is enhance interface dipoles between the high-k dielectric layers and the SiO2 interface layer, but also to well control types and amounts of fixed charges inside the high-k gate dielectric layers, so as to effectively control the threshold voltage of the device.

摘要翻译： 提供了具有通过其栅极堆叠配置控制的阈值电压的CMOSFET器件及其制造方法。 CMOSFET器件包括：半导体衬底; 在硅衬底上生长的界面层; 沉积在界面层上的第一高k栅介质层; 沉积在第一高k栅极电介质层上的非常薄的金属层; 沉积在金属层上的第二高k栅介质层; 以及沉积在第二高k栅极电介质层上的栅电极层。 根据本发明，非常薄的金属层分别沉积在用于NMOS和PMOS器件的高k栅极电介质层之间，使得器件的平带电压通过由 金属层在高k栅极电介质层内，因此控制器件的阈值电压。 因此，不仅可以增强高k电介质层和SiO 2界面层之间的界面偶极子，而且可以很好地控制高k栅极电介质层内的固定电荷的类型和量，以有效地控制 器件的阈值电压。