公开(公告)号：US08482990B2

公开(公告)日：2013-07-09

申请号：US13025872

申请日：2011-02-11

申请人： Hong-Chen Cheng ,  Ming-Yi Lee ,  Kuo-Hua Pan ,  Jung-Hsuan Chen ,  Li-Chun Tien ,  Cheng Hung Lee ,  Hung-Jen Liao

发明人： Hong-Chen Cheng ,  Ming-Yi Lee ,  Kuo-Hua Pan ,  Jung-Hsuan Chen ,  Li-Chun Tien ,  Cheng Hung Lee ,  Hung-Jen Liao

IPC分类号： G11C7/10

CPC分类号： G11C5/06 ,  G11C5/147 ,  G11C5/148 ,  G11C11/417

摘要： A circuit comprises a first PMOS transistor, a second PMOS transistor, a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, and a fourth NMOS transistor. The PMOS transistors and the NMOS transistors are configured to provide a first voltage reference node having a first reference voltage and a second voltage reference node having a second reference voltage. The first reference voltage and the second reference voltage serve as a first reference voltage and a second reference voltage for a memory cell, respectively.

摘要翻译： 电路包括第一PMOS晶体管，第二PMOS晶体管，第一NMOS晶体管，第二NMOS晶体管，第三NMOS晶体管和第四NMOS晶体管。 PMOS晶体管和NMOS晶体管被配置为提供具有第一参考电压的第一电压参考节点和具有第二参考电压的第二参考电压节点。 第一参考电压和第二参考电压分别用作存储器单元的第一参考电压和第二参考电压。

公开(公告)号：US08837250B2

公开(公告)日：2014-09-16

申请号：US12839490

申请日：2010-07-20

申请人： You-Cheng Xiao ,  Hong-Chen Cheng ,  Chung-Ji Lu ,  Cheng Hung Lee ,  Jung-Hsuan Chen ,  Li-Chun Tien

发明人： You-Cheng Xiao ,  Hong-Chen Cheng ,  Chung-Ji Lu ,  Cheng Hung Lee ,  Jung-Hsuan Chen ,  Li-Chun Tien

IPC分类号： G11C8/10

CPC分类号： G11C8/10 ,  G11C11/413

摘要： A word line decoder comprises a plurality of driver circuits, a plurality of word lines provided at respective outputs of the driver circuits, and a plurality of primary input lines coupled to the driver circuits and oriented in a first direction. The word line decoder also comprises a plurality of secondary input lines coupled to the driver circuits and oriented in the first direction. The word line decoder also comprises a local decode line coupled to each of the primary input lines. The word line decoder also comprises a decode line coupled to the local decode line and oriented in the first direction. A cluster decode line is coupled to the decode line. The word line decoder is configured to select at least one of the word lines based on signals provided by the cluster decode line and the secondary input lines.

摘要翻译： 字线解码器包括多个驱动器电路，设置在驱动器电路的各个输出处的多个字线以及耦合到驱动器电路并沿第一方向取向的多个主输入线。 字线解码器还包括耦合到驱动器电路并沿第一方向定向的多个次级输入线。 字线解码器还包括耦合到每个主输入线的本地解码线。 字线解码器还包括耦合到本地解码线并沿第一方向定向的解码线。 集群解码线耦合到解码线。 字线解码器被配置为基于由群集解码线和辅助输入线提供的信号来选择至少一个字线。

公开(公告)号：US08942053B2

公开(公告)日：2015-01-27

申请号：US13535075

申请日：2012-06-27

申请人： Chung-Ji Lu ,  Hung-Jen Liao ,  Cheng Hung Lee ,  Derek C. Tao ,  Annie-Li-Keow Lum ,  Hong-Chen Cheng

发明人： Chung-Ji Lu ,  Hung-Jen Liao ,  Cheng Hung Lee ,  Derek C. Tao ,  Annie-Li-Keow Lum ,  Hong-Chen Cheng

IPC分类号： G11C7/02 ,  G11C7/06

CPC分类号： G11C7/067 ,  G11C7/065

摘要： A circuit includes a first node, a second node, a first current mirror circuit, and a second current mirror circuit. The first current mirror circuit has a reference end and a mirrored end. The reference end of the first current mirror circuit is coupled to the first node, and the mirrored end of the first current mirror circuit is coupled to the second node. The second current mirror circuit has a reference end and a mirrored end. The reference end of the second current mirror circuit is coupled to the second node, and the mirrored end of the second current mirror circuit is coupled to the first node.

摘要翻译： 电路包括第一节点，第二节点，第一电流镜电路和第二电流镜电路。 第一电流镜电路具有参考端和镜像端。 第一电流镜电路的参考端耦合到第一节点，并且第一电流镜电路的镜像端耦合到第二节点。 第二电流镜电路具有参考端和镜像端。 第二电流镜电路的参考端耦合到第二节点，并且第二电流镜电路的镜像端耦合到第一节点。

公开(公告)号：US08355277B2

公开(公告)日：2013-01-15

申请号：US13008992

申请日：2011-01-19

申请人： Hong-Chen Cheng ,  Chih-Chieh Chiu ,  Hsu-Shun Chen ,  Chung-Ji Lu ,  Cheng Hung Lee ,  Hung-Jen Liao

发明人： Hong-Chen Cheng ,  Chih-Chieh Chiu ,  Hsu-Shun Chen ,  Chung-Ji Lu ,  Cheng Hung Lee ,  Hung-Jen Liao

IPC分类号： G11C11/413 ,  G11C5/14

CPC分类号： G11C11/413

摘要： A SRAM system includes: a SRAM cell array coupled between high and low supply nodes, a difference therebetween defining a data retention voltage (VDR) for a low power data retention mode; a main power switch coupling one of high and low supply nodes to a main power supply and disconnecting the one high and low supply nodes from the main power supply during the low power data retention mode; a monitor cell including a SRAM cell preloaded with a data bit and configured for data destruction responsive to a reduction in VDR before data destruction occurs in the SRAM cell array; and a clamping power switch responsive to data destruction in the monitor cell to couple the one of the high and low supply nodes to the main power supply.

摘要翻译： SRAM系统包括：耦合在高电源节点和低电源节点之间的SRAM单元阵列，其间限定用于低功率数据保持模式的数据保持电压（VDR）; 主电源开关将高电源和低电源节点之一耦合到主电源，并且在低功率数据保持模式期间将一个高电源和低电源节点与主电源断开; 监控单元，其包括预先装载有数据位的SRAM单元，并且被配置为在SRAM单元阵列中发生数据破坏之前响应于VDR的减小而进行的数据破坏; 以及钳位电源开关，其响应于监视器单元中的数据破坏，将高电源节点和低电源节点中的一个耦合到主电源。

公开(公告)号：US08223571B2

公开(公告)日：2012-07-17

申请号：US12839575

申请日：2010-07-20

申请人： Chung-Ji Lu ,  Hung-Jen Liao ,  Cheng Hung Lee ,  Derek C. Tao ,  Annie-Li-Keow Lum ,  Hong-Chen Cheng

发明人： Chung-Ji Lu ,  Hung-Jen Liao ,  Cheng Hung Lee ,  Derek C. Tao ,  Annie-Li-Keow Lum ,  Hong-Chen Cheng

IPC分类号： G11C7/02

CPC分类号： G11C7/067 ,  G11C7/065

摘要： A circuit includes a first left transistor having a first left drain, a first left gate, and a first left source; a second left transistor having a second left drain, a second left gate, and a second left source; a third left transistor having a third left drain, a third left gate, and a third left source; a first right transistor having a first right drain, a first right gate, and a first right source; a second right transistor having a second right drain, a second right gate, and a second right source; a third right transistor having a third right drain, a third right gate, and a third right source; a left node electrically coupling the first left drain, the second left drain, the second left gate, the third right gate, and the third left drain; and a right node electrically coupling the first right drain, the second right drain, the second right gate, the third left gate, and the third right drain.

摘要翻译： 电路包括具有第一左漏极，第一左栅极和第一左源的第一左晶体管; 第二左晶体管，具有第二左漏极，第二左栅极和第二左源极; 第三左晶体管，具有第三左漏极，第三左栅极和第三左源; 第一右晶体管，具有第一右漏极，第一右栅极和第一右源; 第二右晶体管，具有第二右漏极，第二右栅极和第二右源; 第三右晶体管，具有第三右漏极，第三右栅极和第三右源; 左节点，电耦合第一左排水口，第二左排水管，第二左闸门，第三右闸门和第三左排水管; 以及电连接第一右排水管，第二右排水管，第二右浇口，第三左浇口和第三右排水沟的右节点。

公开(公告)号：US20120020176A1

公开(公告)日：2012-01-26

申请号：US12839575

申请日：2010-07-20

申请人： Chung-Ji Lu ,  Hung-Jen Liao ,  Cheng Hung Lee ,  Derek C. Tao ,  Annie-Li-Keow Lum ,  Hong-Chen Cheng

发明人： Chung-Ji Lu ,  Hung-Jen Liao ,  Cheng Hung Lee ,  Derek C. Tao ,  Annie-Li-Keow Lum ,  Hong-Chen Cheng

IPC分类号： G11C7/06 ,  H03F3/45

CPC分类号： G11C7/067 ,  G11C7/065

摘要： Some embodiments regard a circuit comprising: a first left transistor having a first left drain, a first left gate, and a first left source; a second left transistor having a second left drain, a second left gate, and a second left source; a third left transistor having a third left drain, a third left gate, and a third left source; a first right transistor having a first right drain, a first right gate, and a first right source; a second right transistor having a second right drain, a second right gate, and a second right source; a third right transistor having a third right drain, a third right gate, and a third right source; a left node electrically coupling the first left drain, the second left drain, the second left gate, the third right gate, and the third left drain; and a right node electrically coupling the first right drain, the second right drain, the second right gate, the third left gate, and the third right drain.

摘要翻译： 一些实施例涉及一种电路，包括：具有第一左漏极，第一左栅极和第一左源的第一左晶体管; 第二左晶体管，具有第二左漏极，第二左栅极和第二左源极; 第三左晶体管，具有第三左漏极，第三左栅极和第三左源; 第一右晶体管，具有第一右漏极，第一右栅极和第一右源; 第二右晶体管，具有第二右漏极，第二右栅极和第二右源; 第三右晶体管，具有第三右漏极，第三右栅极和第三右源; 左节点，电耦合第一左排水口，第二左排水管，第二左闸门，第三右闸门和第三左排水管; 以及电连接第一右排水管，第二右排水管，第二右浇口，第三左浇口和第三右排水沟的右节点。

公开(公告)号：US08792292B2

公开(公告)日：2014-07-29

申请号：US13046625

申请日：2011-03-11

申请人： Hong-Chen Cheng ,  Jung-Ping Yang ,  Chung-Ji Lu ,  Derek C. Tao ,  Cheng Hung Lee ,  Hung-Jen Liao

发明人： Hong-Chen Cheng ,  Jung-Ping Yang ,  Chung-Ji Lu ,  Derek C. Tao ,  Cheng Hung Lee ,  Hung-Jen Liao

IPC分类号： G11C29/00

CPC分类号： G11C29/846

摘要： A circuit includes a failure address register configured to store a first row address, a row address modifier coupled to the failure address register, wherein the row address modifier is configured to modify the first row address received from the failure address register to generate a second row address. A first comparator is configured to receive and compare the first row address and a third row address. A second comparator is configured to receive and compare the second row address and the third row address. The first and the second row addresses are failed row addresses in a memory.

摘要翻译： 电路包括被配置为存储第一行地址的故障地址寄存器，耦合到故障地址寄存器的行地址修改器，其中行地址修改器被配置为修改从故障地址寄存器接收的第一行地址以生成第二行 地址。 第一比较器被配置为接收和比较第一行地址和第三行地址。 第二比较器被配置为接收和比较第二行地址和第三行地址。 第一行地址和第二行地址是存储器中的失败行地址。

公开(公告)号：US20120230127A1

公开(公告)日：2012-09-13

申请号：US13046625

申请日：2011-03-11

申请人： Hong-Chen Cheng ,  Jung-Ping Yang ,  Chung-Ji Lu ,  Derek C. Tao ,  Cheng Hung Lee ,  Hung-Jen Liao

发明人： Hong-Chen Cheng ,  Jung-Ping Yang ,  Chung-Ji Lu ,  Derek C. Tao ,  Cheng Hung Lee ,  Hung-Jen Liao

IPC分类号： G11C29/04

CPC分类号： G11C29/846

摘要： A circuit includes a failure address register configured to store a first row address, a row address modifier coupled to the failure address register, wherein the row address modifier is configured to modify the first row address received from the failure address register to generate a second row address. A first comparator is configured to receive and compare the first row address and a third row address. A second comparator is configured to receive and compare the second row address and the third row address. The first and the second row addresses are failed row addresses in a memory.

摘要翻译： 电路包括被配置为存储第一行地址的故障地址寄存器，耦合到故障地址寄存器的行地址修改器，其中行地址修改器被配置为修改从故障地址寄存器接收的第一行地址以生成第二行 地址。 第一比较器被配置为接收和比较第一行地址和第三行地址。 第二比较器被配置为接收和比较第二行地址和第三行地址。 第一行地址和第二行地址是存储器中的失败行地址。

公开(公告)号：US07848174B2

公开(公告)日：2010-12-07

申请号：US12126780

申请日：2008-05-23

申请人： Hong-Chen Cheng ,  Hung-Jen Liao ,  Cheng Hung Lee ,  Ruei-Je Tsai

发明人： Hong-Chen Cheng ,  Hung-Jen Liao ,  Cheng Hung Lee ,  Ruei-Je Tsai

IPC分类号： G11C8/00 ,  G11C7/00

CPC分类号： G11C11/18 ,  G11C11/413

摘要： A word-line tracking system for a memory array having a plurality of memory cells, the word-line tracking system comprises a dummy row having substantially identical structure as one or more regular rows of the memory cells, the dummy row including a dummy word-line having a first and a second end at the opposite longitudinal ends of the dummy word-line, the first end being connected to a word-line driver, a self timing generator configured to receive a clock signal and generate a pulse signal in sync with the clock signal for the dummy word-line driver, the self timing generator having a first terminal for receiving a feedback signal to determine the falling edge of the pulse signal, a voltage-to-current converter connected to the second end of the dummy word-line, a current-to-voltage converter connected to the feedback terminal, and a wire connecting the voltage-to-current converter to the current-to-voltage converter.

摘要翻译： 一种用于具有多个存储单元的存储器阵列的字线跟踪系统，该字线跟踪系统包括具有与存储器单元的一个或多个规则行基本相同结构的虚拟行，该虚拟行包括一个虚拟字 - 所述线在所述虚拟字线的相对的纵向端具有第一端和第二端，所述第一端连接到字线驱动器，自定时发生器被配置为接收时钟信号并与 用于虚拟字线驱动器的时钟信号，自定时发生器具有用于接收反馈信号以确定脉冲信号的下降沿的第一端子，连接到虚拟字的第二端的电压 - 电流转换器 线路，连接到反馈端子的电流 - 电压转换器以及将电压 - 电流转换器连接到电流 - 电压转换器的导线。

公开(公告)号：US20090290446A1

公开(公告)日：2009-11-26

申请号：US12126780

申请日：2008-05-23

申请人： Hong-Chen Cheng ,  Hung-Jen Liao ,  Cheng Hung Lee ,  Ruei-Je Tsai

发明人： Hong-Chen Cheng ,  Hung-Jen Liao ,  Cheng Hung Lee ,  Ruei-Je Tsai

IPC分类号： G11C8/18

CPC分类号： G11C11/18 ,  G11C11/413

摘要： A word-line tracking system for a memory array having a plurality of memory cells, the word-line tracking system comprises a dummy row having substantially identical structure as one or more regular rows of the memory cells, the dummy row including a dummy word-line having a first and a second end at the opposite longitudinal ends of the dummy word-line, the first end being connected to a word-line driver, a self timing generator configured to receive a clock signal and generate a pulse signal in sync with the clock signal for the dummy word-line driver, the self timing generator having a first terminal for receiving a feedback signal to determine the falling edge of the pulse signal, a voltage-to-current converter connected to the second end of the dummy word-line, a current-to-voltage converter connected to the feedback terminal, and a wire connecting the voltage-to-current converter to the current-to-voltage converter.

摘要翻译： 一种用于具有多个存储单元的存储器阵列的字线跟踪系统，该字线跟踪系统包括具有与存储器单元的一个或多个规则行基本相同结构的虚拟行，该虚拟行包括一个虚拟字 - 所述线在所述虚拟字线的相对的纵向端具有第一端和第二端，所述第一端连接到字线驱动器，自定时发生器被配置为接收时钟信号并与 用于虚拟字线驱动器的时钟信号，自定时发生器具有用于接收反馈信号以确定脉冲信号的下降沿的第一端子，连接到虚拟字的第二端的电压 - 电流转换器 线路，连接到反馈端子的电流 - 电压转换器以及将电压 - 电流转换器连接到电流 - 电压转换器的导线。