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    THIN-FILM TRANSISTOR, ARRAY SUBSTRATE HAVING THE THIN-FILM TRANSISTOR AND METHOD OF MANUFACTURING THE ARRAY SUBSTRATE
    2.
    发明申请
    THIN-FILM TRANSISTOR, ARRAY SUBSTRATE HAVING THE THIN-FILM TRANSISTOR AND METHOD OF MANUFACTURING THE ARRAY SUBSTRATE 有权
    薄膜晶体管，具有薄膜晶体管的阵列基板和制造阵列基板的方法

    公开(公告)号：US20110140103A1

    公开(公告)日：2011-06-16

    申请号：US13030213

    申请日：2011-02-18

    申请人： Je-Hun LEE ,  Do-Hyun KIM ,  Eun-Guk LEE ,  Chang-OH JEONG

    发明人： Je-Hun LEE ,  Do-Hyun KIM ,  Eun-Guk LEE ,  Chang-OH JEONG

    IPC分类号： H01L29/786 ,  H01L21/336

    CPC分类号： H01L29/7869 ,  H01L27/1214 ,  H01L27/1225 ,  H01L27/124 ,  H01L27/1288

    摘要： A thin-film transistor includes a semiconductor pattern, source and drain electrodes and a gate electrode, the semiconductor pattern is formed on a base substrate, and the semiconductor pattern includes metal oxide. The source and drain electrodes are formed on the semiconductor pattern such that the source and drain electrodes are spaced apart from each other and an outline of the source and drain electrodes is substantially same as an outline of the semiconductor pattern. The gate electrode is disposed in a region between the source and drain electrodes such that portions of the gate electrode are overlapped with the source and drain electrodes. Therefore, leakage current induced by light is minimized. As a result, characteristics of the thin-film transistor are enhanced, after-image is reduced to enhance display quality, and stability of manufacturing process is enhanced.

    摘要翻译： 薄膜晶体管包括半导体图案，源极和漏极以及栅极，半导体图案形成在基底基板上，半导体图案包括金属氧化物。 源极和漏极形成在半导体图案上，使得源极和漏极彼此间隔开，并且源极和漏极的轮廓与半导体图案的轮廓基本相同。 栅电极设置在源电极和漏电极之间的区域中，使得栅电极的一部分与源电极和漏电极重叠。 因此，由光引起的漏电流最小化。 结果，增强了薄膜晶体管的特性，减少了后图像以提高显示质量，并且提高了制造工艺的稳定性。

    THIN-FILM TRANSISTOR, ARRAY SUBSTRATE HAVING THE THIN-FILM TRANSISTOR AND METHOD OF MANUFACTURING THE ARRAY SUBSTRATE
    3.
    发明申请
    THIN-FILM TRANSISTOR, ARRAY SUBSTRATE HAVING THE THIN-FILM TRANSISTOR AND METHOD OF MANUFACTURING THE ARRAY SUBSTRATE 有权
    薄膜晶体管，具有薄膜晶体管的阵列基板和制造阵列基板的方法

    公开(公告)号：US20080308826A1

    公开(公告)日：2008-12-18

    申请号：US11930502

    申请日：2007-10-31

    申请人： Je-Hun LEE ,  Do-Hyun KIM ,  Eun-Guk LEE ,  Chang-Oh JEONG

    发明人： Je-Hun LEE ,  Do-Hyun KIM ,  Eun-Guk LEE ,  Chang-Oh JEONG

    IPC分类号： H01L29/78 ,  H01L21/02

    CPC分类号： H01L29/7869 ,  H01L27/1214 ,  H01L27/1225 ,  H01L27/124 ,  H01L27/1288

    摘要： A thin-film transistor includes a semiconductor pattern, source and drain electrodes and a gate electrode, the semiconductor pattern is formed on a base substrate, and the semiconductor pattern includes metal oxide. The source and drain electrodes are formed on the semiconductor pattern such that the source and drain electrodes are spaced apart from each other and an outline of the source and drain electrodes is substantially same as an outline of the semiconductor pattern. The gate electrode is disposed in a region between the source and drain electrodes such that portions of the gate electrode are overlapped with the source and drain electrodes. Therefore, leakage current induced by light is minimized. As a result, characteristics of the thin-film transistor are enhanced, after-image is reduced to enhance display quality, and stability of manufacturing process is enhanced.

    摘要翻译： 薄膜晶体管包括半导体图案，源极和漏极以及栅极，半导体图案形成在基底基板上，半导体图案包括金属氧化物。 源极和漏极形成在半导体图案上，使得源极和漏极彼此间隔开，并且源极和漏极的轮廓与半导体图案的轮廓基本相同。 栅电极设置在源电极和漏电极之间的区域中，使得栅电极的一部分与源电极和漏电极重叠。 因此，由光引起的漏电流最小化。 结果，增强了薄膜晶体管的特性，减少了后图像以提高显示质量，并且提高了制造工艺的稳定性。

    THIN FILM TRANSISTOR SUBSTRATE AND FABRICATING METHOD THEREOF
    5.
    发明申请
    THIN FILM TRANSISTOR SUBSTRATE AND FABRICATING METHOD THEREOF 审中-公开
    薄膜晶体管基板及其制造方法

    公开(公告)号：US20080099765A1

    公开(公告)日：2008-05-01

    申请号：US11923914

    申请日：2007-10-25

    申请人： Do-Hyun KIM ,  Je-Hun LEE ,  Chang-Oh JEONG

    发明人： Do-Hyun KIM ,  Je-Hun LEE ,  Chang-Oh JEONG

    IPC分类号： H01L29/04 ,  H01L21/336

    CPC分类号： H01L29/4908 ,  H01L27/124 ,  H01L29/458

    摘要： A thin film transistor substrate and fabricating method thereof, the thin film transistor substrate including a substrate, a gate line and a gate electrode, each including a metal adhesion layer and a Cu alloy layer disposed on the substrate, an active layer and an ohmic contact layer disposed over the gate electrode, a gate insulating layer disposed between the gate electrode and the active and ohmic contact layers, source and drain electrodes disposed on the ohmic contact layer, and a data line connected to the source electrode.

    摘要翻译： 一种薄膜晶体管基板及其制造方法，所述薄膜晶体管基板包括基板，栅极线和栅电极，每个薄膜晶体管基板包括设置在基板上的金属粘合层和Cu合金层，有源层和欧姆接触 设置在栅极电极上的栅极绝缘层，设置在栅电极与有源欧姆接触层之间的栅极绝缘层，设置在欧姆接触层上的源电极和漏电极以及连接到源电极的数据线。

    ARRAY SUBSTRATE, DISPLAY DEVICE HAVING THE SAME AND METHOD OF MANUFACTURING THE SAME
    6.
    发明申请
    ARRAY SUBSTRATE, DISPLAY DEVICE HAVING THE SAME AND METHOD OF MANUFACTURING THE SAME 失效
    阵列基板，具有该基板的显示装置及其制造方法

    公开(公告)号：US20080017862A1

    公开(公告)日：2008-01-24

    申请号：US11779534

    申请日：2007-07-18

    申请人： Je-Hun LEE ,  Do-Hyun KIM ,  Eun-Guk LEE ,  Chang-Oh JEONG

    发明人： Je-Hun LEE ,  Do-Hyun KIM ,  Eun-Guk LEE ,  Chang-Oh JEONG

    IPC分类号： H01L29/04 ,  H01L21/00

    CPC分类号： G02F1/136286 ,  G02F2001/13629 ,  G02F2001/136295 ,  H01L27/124

    摘要： An array substrate includes a switching element, a signal transmission line, a passivation layer and a pixel electrode. The switching element is disposed on an insulating substrate. The signal transmission line is connected to the switching element and includes a barrier layer, a conductive line, and a copper nitride layer. The barrier layer is disposed on the insulating substrate. The conductive line is disposed on the barrier layer and includes copper or copper alloy. The copper nitride layer covers the conductive line. The passivation layer covers the switching element and the signal transmission line and has a contact hole through which a drain electrode of the switching element is partially exposed. The pixel electrode is disposed on the insulating substrate, and is connected to the drain electrode of the switching element through the contact hole.

    摘要翻译： 阵列基板包括开关元件，信号传输线，钝化层和像素电极。 开关元件设置在绝缘基板上。 信号传输线连接到开关元件，并且包括阻挡层，导电线和氮化铜层。 阻挡层设置在绝缘基板上。 导电线设置在阻挡层上并且包括铜或铜合金。 氮化铜层覆盖导电线。 钝化层覆盖开关元件和信号传输线，并且具有接触孔，开关元件的漏电极通过该接触孔部分露出。 像素电极设置在绝缘基板上，并通过接触孔与开关元件的漏电极连接。

    ARRAY SUBSTRATE, DISPLAY DEVICE HAVING THE SAME AND METHOD OF MANUFACTURING THE SAME
    7.
    发明申请
    ARRAY SUBSTRATE, DISPLAY DEVICE HAVING THE SAME AND METHOD OF MANUFACTURING THE SAME 审中-公开
    阵列基板，具有该基板的显示装置及其制造方法

    公开(公告)号：US20110309510A1

    公开(公告)日：2011-12-22

    申请号：US13222558

    申请日：2011-08-31

    申请人： Je-Hun LEE ,  Do-Hyun KIM ,  Eun-Guk LEE ,  Chang-Oh JEONG

    发明人： Je-Hun LEE ,  Do-Hyun KIM ,  Eun-Guk LEE ,  Chang-Oh JEONG

    IPC分类号： H01L23/482

    CPC分类号： G02F1/136286 ,  G02F2001/13629 ,  G02F2001/136295 ,  H01L27/124

    摘要： An array substrate includes a switching element, a signal transmission line, a passivation layer and a pixel electrode. The switching element is disposed on an insulating substrate. The signal transmission line is connected to the switching element and includes a barrier layer, a conductive line, and a copper nitride layer. The barrier layer is disposed on the insulating substrate. The conductive line is disposed on the barrier layer and includes copper or copper alloy. The copper nitride layer covers the conductive line. The passivation layer covers the switching element and the signal transmission line and has a contact hole through which a drain electrode of the switching element is partially exposed. The pixel electrode is disposed on the insulating substrate, and is connected to the drain electrode of the switching element through the contact hole.

    摘要翻译： 阵列基板包括开关元件，信号传输线，钝化层和像素电极。 开关元件设置在绝缘基板上。 信号传输线连接到开关元件，并且包括阻挡层，导电线和氮化铜层。 阻挡层设置在绝缘基板上。 导电线设置在阻挡层上并且包括铜或铜合金。 氮化铜层覆盖导电线。 钝化层覆盖开关元件和信号传输线，并且具有接触孔，开关元件的漏电极通过该接触孔部分露出。 像素电极设置在绝缘基板上，并通过接触孔与开关元件的漏电极连接。

    THIN FILM TRANSISTOR ARRAY PANEL AND MANUFACTURING METHOD THEREOF
    10.
    发明申请
    THIN FILM TRANSISTOR ARRAY PANEL AND MANUFACTURING METHOD THEREOF 失效
    薄膜晶体管阵列及其制造方法

    公开(公告)号：US20120315731A1

    公开(公告)日：2012-12-13

    申请号：US13523767

    申请日：2012-06-14

    申请人： Je-Hun LEE ,  Sung-Jin KIM ,  Hee-Joon KIM ,  Chang-Oh JEONG

    发明人： Je-Hun LEE ,  Sung-Jin KIM ,  Hee-Joon KIM ,  Chang-Oh JEONG

    IPC分类号： H01L21/336

    CPC分类号： G02F1/13439 ,  G02F1/13458 ,  H01L27/12 ,  H01L27/124 ,  H01L29/458 ,  H01L29/4908

    摘要： A thin film transistor array panel is provided, which includes a plurality of gate line, a plurality of common electrodes, a gate insulating layer covering the gate lines and the common electrodes, a plurality of semiconductor layers formed on the gate insulating layer, a plurality of data lines including a plurality of source electrodes and formed on the semiconductor layer, a plurality of drain electrodes formed on the semiconductor layer, and a plurality of pixel electrodes overlapping the common electrodes and connected to the drain electrodes. Because the common electrodes are made of ITON, IZON, or a-ITON, or a double layer of ITO/ITON, IZO/IZON, or a-a-ITO/a-ITON, when H2 or SiH4 are injected to form a silicon nitride (SiNX) layer on the common electrodes, the opaque metal Sn or Zn is not produced on the surfaces of the common electrode.

    摘要翻译： 提供薄膜晶体管阵列面板，其包括多个栅极线，多个公共电极，覆盖栅极线和公共电极的栅极绝缘层，形成在栅极绝缘层上的多个半导体层，多个 包括多个源电极并形成在半导体层上的数据线，形成在半导体层上的多个漏电极以及与公共电极重叠并连接到漏电极的多个像素电极。 由于公共电极由ITON，IZON或者-IONON制成，或者是将双重层的ITO / ITON，IZO / IZON或者a-ITO / a-ITON，当注入H 2或SiH 4以形成氮化硅时 SiNX）层，在公共电极的表面上不产生不透明金属Sn或Zn。