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    Method for manufacturing thin film transistor array panel
    2.
    发明授权
    Method for manufacturing thin film transistor array panel 有权
    制造薄膜晶体管阵列面板的方法

    公开(公告)号：US08557621B2

    公开(公告)日：2013-10-15

    申请号：US13157806

    申请日：2011-06-10

    Applicant: Jong-Hyun Choung ,  Yang Ho Bae ,  Jean Ho Song ,  O Sung Seo ,  Sun-Young Hong ,  Hwa Yeul Oh ,  Bong-Kyun Kim ,  Nam Seok Suh ,  Dong-Ju Yang ,  Wang Woo Lee

    Inventor： Jong-Hyun Choung ,  Yang Ho Bae ,  Jean Ho Song ,  O Sung Seo ,  Sun-Young Hong ,  Hwa Yeul Oh ,  Bong-Kyun Kim ,  Nam Seok Suh ,  Dong-Ju Yang ,  Wang Woo Lee

    IPC: H01L21/00

    CPC classification number: H01L21/32134 ,  G02F1/136227 ,  H01L27/1288 ,  H01L29/41733

    Abstract: A method for manufacturing a thin film transistor array panel, including: sequentially forming a first silicon layer, a second silicon layer, a lower metal layer, and an upper metal layer on a gate insulating layer and a gate line; forming a first film pattern on the upper metal layer; forming a first lower metal pattern and a first upper metal pattern that includes a protrusion, by etching the upper metal layer and the lower metal layer; forming first and second silicon patterns by etching the first and second silicon layers; forming a second film pattern by ashing the first film pattern; forming a second upper metal pattern by etching the first upper metal pattern; forming a data line and a thin film transistor by etching the first lower metal pattern and the first and second silicon patterns; and forming a passivation layer and a pixel electrode on the resultant.

    Abstract translation: 一种制造薄膜晶体管阵列面板的方法，包括：在栅绝缘层和栅极线上依次形成第一硅层，第二硅层，下金属层和上金属层; 在上金属层上形成第一膜图案; 通过蚀刻上金属层和下金属层，形成第一下金属图案和包括突起的第一上金属图案; 通过蚀刻第一和第二硅层形成第一和第二硅图案; 通过灰化第一膜图案形成第二膜图案; 通过蚀刻第一上金属图案形成第二上金属图案; 通过蚀刻第一下金属图案和第一和第二硅图案来形成数据线和薄膜晶体管; 并在所得物上形成钝化层和像素电极。

    THIN FILM TRANSISTOR ARRAY PANEL AND METHOD OF MANUFACTURING THE SAME
    7.
    发明申请
    THIN FILM TRANSISTOR ARRAY PANEL AND METHOD OF MANUFACTURING THE SAME 审中-公开
    薄膜晶体管阵列及其制造方法

    公开(公告)号：US20100051934A1

    公开(公告)日：2010-03-04

    申请号：US12504483

    申请日：2009-07-16

    Applicant: Jong-Hyun Choung ,  Bong-Kyun Kim ,  Byeong-Jin Lee ,  Sun-Young Hong ,  Pil-Sang Yun ,  Hong-Sick Park ,  Dong-Ju Yang ,  Young-Joo Choi ,  Nam-Seok Suh

    Inventor： Jong-Hyun Choung ,  Bong-Kyun Kim ,  Byeong-Jin Lee ,  Sun-Young Hong ,  Pil-Sang Yun ,  Hong-Sick Park ,  Dong-Ju Yang ,  Young-Joo Choi ,  Nam-Seok Suh

    IPC: H01L29/786 ,  H01L21/336

    CPC classification number: H01L29/7869 ,  H01L27/1225 ,  H01L27/124 ,  H01L27/1288

    Abstract: A thin film transistor array panel and a method of manufacturing the same are provided according to one or more embodiments. In an embodiment, a method includes: forming a gate line on an insulation substrate; stacking a gate insulating layer, an oxide semiconductor layer, a first barrier layer, and a first copper layer on the gate line; performing a photolithography process on the oxide semiconductor layer, the first barrier layer, and the first copper layer and forming a data line including a source electrode, a drain electrode, and an oxide semiconductor pattern; forming a passivation layer having the contact hole that exposes the drain electrode on the data line and the drain electrode; and forming a pixel electrode that is connected to the drain electrode through the contact hole on the passivation layer, wherein the forming of a data line, a drain electrode, and an oxide semiconductor pattern includes wet etching the first copper layer and then wet etching the first barrier layer and the oxide semiconductor layer.

    Abstract translation: 根据一个或多个实施例提供薄膜晶体管阵列面板及其制造方法。 在一个实施例中，一种方法包括：在绝缘基板上形成栅极线; 在栅极线上堆叠栅极绝缘层，氧化物半导体层，第一势垒层和第一铜层; 在所述氧化物半导体层，所述第一阻挡层和所述第一铜层上进行光刻工艺，并形成包括源电极，漏电极和氧化物半导体图案的数据线; 形成具有使数据线和漏电极上的漏电极露出的接触孔的钝化层; 以及形成通过钝化层上的接触孔连接到漏电极的像素电极，其中数据线，漏电极和氧化物半导体图案的形成包括湿蚀刻第一铜层，然后湿蚀刻 第一阻挡层和氧化物半导体层。

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