公开(公告)号：US08878337B1

公开(公告)日：2014-11-04

申请号：US13186279

申请日：2011-07-19

申请人： Hong-Tsz Pan ,  Yun Wu ,  Shuxian Wu ,  Qi Lin ,  Bang-Thu Nguyen

发明人： Hong-Tsz Pan ,  Yun Wu ,  Shuxian Wu ,  Qi Lin ,  Bang-Thu Nguyen

IPC分类号： H01L21/02

CPC分类号： H01L29/94 ,  H01L21/3212 ,  H01L21/823842 ,  H01L27/0629 ,  H01L29/66181 ,  H01L29/66545 ,  H01L29/78

摘要： A method and integrated circuit structure for mitigating metal gate dishing resulting from chemical mechanical polishing. The integrated circuit structure comprises a first area comprising at least one first type device; a second area comprising at least one second type device; a third area comprising at least one capacitor having an uppermost layer of polysilicon, where the capacitor area is greater than a sum of the first and second areas. The method utilizes the polysilicon of the capacitor to mitigate metal gate dishing of a metal gate of at least one device.

摘要翻译： 一种用于减轻由化学机械抛光引起的金属栅极凹陷的方法和集成电路结构。 集成电路结构包括包括至少一个第一类型装置的第一区域; 第二区域，包括至少一个第二类型装置; 第三区域包括至少一个具有多晶硅最上层的电容器，其中电容器面积大于第一和第二区域的总和。 该方法利用电容器的多晶硅来减轻至少一个器件的金属栅极的金属栅极凹陷。

公开(公告)号：US08350365B1

公开(公告)日：2013-01-08

申请号：US13005680

申请日：2011-01-13

申请人： Yun Wu ,  Hong-Tsz Pan ,  Qi Lin ,  Bang-Thu Nguyen

发明人： Yun Wu ,  Hong-Tsz Pan ,  Qi Lin ,  Bang-Thu Nguyen

IPC分类号： H01L21/4763

CPC分类号： H01L21/266 ,  H01L21/26513

摘要： A hard implantation mask layer is formed on a semiconductor wafer. An etch mask layer is formed on the hard implantation mask layer and patterned. The hard implantation mask layer is etched to form a well implantation pattern and ions are implanted into the semiconductor wafer to form wells in the semiconductor wafer, in areas where the semiconductor wafer is not covered by the well implantation mask.

摘要翻译： 在半导体晶片上形成硬注入掩模层。 在硬注入掩模层上形成蚀刻掩模层并进行图案化。 蚀刻硬注入掩模层以形成良好注入图案，并且在半导体晶片未被阱注入掩模覆盖的区域中，将离子注入到半导体晶片中以在半导体晶片中形成阱。

公开(公告)号：US08890164B1

公开(公告)日：2014-11-18

申请号：US13416297

申请日：2012-03-09

申请人： Hong-Tsz Pan ,  Qi Lin ,  Yun Wu ,  Bang-Thu Nguyen

发明人： Hong-Tsz Pan ,  Qi Lin ,  Yun Wu ,  Bang-Thu Nguyen

IPC分类号： H01L27/108

CPC分类号： H01L27/0928 ,  H01L21/823493 ,  H01L21/823892 ,  H01L27/0255 ,  H01L27/088

摘要： A metal oxide semiconductor field effect transistor (MOSFET) for an integrated circuit includes a substrate of a first conductivity type, a first well region of a second conductivity type located in the substrate, and a second well region of the second conductivity type located within the substrate. The second well region is functionally connected to the first well region, and the second well region has a surface area greater than a surface area of the first well region. The MOSFET further includes a source of the first conductivity type located in the first well region, a drain of the first conductivity type located in the first well region, a substrate terminal of the second conductivity type located in the first well region, a gate oxide on a top surface of the first well region, and a gate electrode located on a top surface of the gate oxide.

摘要翻译： 用于集成电路的金属氧化物半导体场效应晶体管（MOSFET）包括第一导电类型的衬底，位于衬底中的第二导电类型的第一阱区和位于衬底内的第二导电类型的第二阱区 基质。 第二阱区域功能上连接到第一阱区域，并且第二阱区域具有大于第一阱区域的表面积的表面积。 MOSFET还包括位于第一阱区域中的第一导电类型的源极，位于第一阱区域中的第一导电类型的漏极，位于第一阱区域中的第二导电类型的衬底端子，栅极氧化物 在第一阱区的顶表面上，以及栅电极，位于栅极氧化物的顶表面上。

公开(公告)号：US07673270B1

公开(公告)日：2010-03-02

申请号：US11717811

申请日：2007-03-13

申请人： Yan Wang ,  Nui Chong ,  Hong-Tsz Pan ,  Bang-Thu Nguyen ,  Jonathan Jung-Ching Ho ,  Qi Lin ,  Yuhao Luo ,  Hing Yee Angela Wong ,  Xin X. Wu ,  Yuezhen Fan

发明人： Yan Wang ,  Nui Chong ,  Hong-Tsz Pan ,  Bang-Thu Nguyen ,  Jonathan Jung-Ching Ho ,  Qi Lin ,  Yuhao Luo ,  Hing Yee Angela Wong ,  Xin X. Wu ,  Yuezhen Fan

IPC分类号： G06F17/50

CPC分类号： G03F1/36

摘要： Method and apparatus for compensating an integrated circuit design for mechanical stress effects. One aspect of the invention relates to designing an integrated circuit. Layout data is obtained that describes layers of the integrated circuit. At least one of the layers is analyzed to detect at least one structure susceptible to damage from mechanical stress. A bias is automatically added to each of the at least one structure to reduce mechanical stress of the at least one structure as fabricated. Augmented layout data is then provided for the integrated circuit.

摘要翻译： 用于补偿机械应力作用的集成电路设计的方法和装置。 本发明的一个方面涉及集成电路的设计。 获得描述集成电路层的布局数据。 分析至少一层以检测易受机械应力破坏的至少一种结构。 偏置被自动地添加到至少一个结构中的每个结构中，以减少所制造的至少一个结构的机械应力。 然后为集成电路提供增强的布局数据。

公开(公告)号：US08350253B1

公开(公告)日：2013-01-08

申请号：US12697027

申请日：2010-01-29

申请人： Bei Zhu ,  Hong-Tze Pan ,  Bang-Thu Nguyen ,  Qi Lin ,  Zhiyuan Wu ,  Ping-Chin Yeh ,  Jae-Gyung Ahn ,  Yun Wu

发明人： Bei Zhu ,  Hong-Tze Pan ,  Bang-Thu Nguyen ,  Qi Lin ,  Zhiyuan Wu ,  Ping-Chin Yeh ,  Jae-Gyung Ahn ,  Yun Wu

IPC分类号： H01L29/06

CPC分类号： H01L29/66636 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823864 ,  H01L29/6653 ,  H01L29/7848

摘要： An integrated circuit (“IC”) fabricated on a semiconductor substrate has an active gate structure formed over a channel region in the semiconductor substrate. A dummy gate structure is formed on a dielectric isolation structure. The dummy gate structure and the active gate structure have the same width. A sidewall spacer on the dummy gate structure overlies a semiconductor portion between a strain-inducing insert and the dielectric isolation structure.

摘要翻译： 在半导体衬底上制造的集成电路（IC）具有形成在半导体衬底中的沟道区上的有源栅极结构。 在绝缘隔离结构上形成虚拟栅极结构。 虚拟栅极结构和有源栅极结构具有相同的宽度。 虚拟栅极结构上的侧壁间隔物覆盖在应变诱导插入件和介电隔离结构之间的半导体部分。

公开(公告)号：US08063654B2

公开(公告)日：2011-11-22

申请号：US12505215

申请日：2009-07-17

申请人： Arifur Rahman ,  Hong-Tsz Pan ,  Bang-Thu Nguyen

发明人： Arifur Rahman ,  Hong-Tsz Pan ,  Bang-Thu Nguyen

IPC分类号： G01R31/26

CPC分类号： G01R31/318544 ,  H01L2224/16145

摘要： An integrated circuit device includes a stacked die and a base die having probe pads that directly couple to test logic of the base die to implement a scan chain for testing of the integrated circuit device. The base die further includes contacts disposed on a back side of the base die and through-die vias coupled to the contacts and coupled to programmable logic of the base die. The base die also includes a first probe pad configured to couple test input, a second probe pad configured to couple test output, and a third probe pad configured to couple control signals. Test logic of the base die is configured to couple to additional test logic of the stacked die to implement the scan chain. The probe pads are coupled directly to the test logic such that configuration of the programmable logic is not required to implement the scan chain.

摘要翻译： 集成电路器件包括堆叠管芯和具有探针焊盘的基座，该探针焊盘直接耦合到基座芯片的测试逻辑，以实现用于集成电路器件测试的扫描链。 基模还包括设置在基模的背面上的触点和耦合到触点并连接到基模的可编程逻辑的通孔通孔。 基座芯片还包括被配置为耦合测试输入的第一探针焊盘，被配置为耦合测试输出的第二探针焊盘和被配置为耦合控制信号的第三探测焊盘。 基准芯片的测试逻辑被配置为耦合到堆叠芯片的附加测试逻辑以实现扫描链。 探针焊盘直接耦合到测试逻辑，使得不需要可编程逻辑的配置来实现扫描链。

公开(公告)号：US20110012633A1

公开(公告)日：2011-01-20

申请号：US12505215

申请日：2009-07-17

申请人： Arifur Rahman ,  Hong-Tsz Pan ,  Bang-Thu Nguyen

发明人： Arifur Rahman ,  Hong-Tsz Pan ,  Bang-Thu Nguyen

IPC分类号： G01R31/02

CPC分类号： G01R31/318544 ,  H01L2224/16145

摘要： An integrated circuit device is described that includes a stacked die and a base die having probe pads that directly couple to test logic of the base die so as to implement a scan chain for testing of the integrated circuit device. The base die further includes contacts disposed on a back side of the base die and through-die vias coupled to the contacts and coupled to programmable logic of the base die. In addition, the base die includes a first probe pad configured to couple test input, a second probe pad configured to couple test output and a third probe pad configured to couple control signals. Test logic of the base die is configured to couple to additional test logic of the stacked die so as to implement a scan chain for testing of the integrated circuit device. In accordance with aspects of the present invention, the first probe pad, the second probe pad and the third probe pad are coupled directly to the test logic such that configuration of the programmable logic is not required for coupling the test input, the test output and the control signal between the base die and the stacked die so as to implement the scan chain.

摘要翻译： 描述了一种集成电路器件，其包括具有探针焊盘的堆叠管芯和基座管芯，所述探针焊盘直接耦合到所述基座管芯的测试逻辑，以便实现用于所述集成电路器件的测试的扫描链。 基模还包括设置在基模的背面上的触点和耦合到触点并连接到基模的可编程逻辑的通孔通孔。 此外，基座芯片包括被配置为耦合测试输入的第一探针焊盘，被配置为耦合测试输出的第二探针焊盘和被配置为耦合控制信号的第三探针焊盘。 基模的测试逻辑被配置为耦合到堆叠管芯的附加测试逻辑，以便实现用于集成电路器件测试的扫描链。 根据本发明的方面，第一探针焊盘，第二探针焊盘和第三探针焊盘直接耦合到测试逻辑，使得不需要可编程逻辑的配置来耦合测试输入，测试输出和 基模和堆叠管芯之间的控制信号，以实现扫描链。

公开(公告)号：US08266553B1

公开(公告)日：2012-09-11

申请号：US12141543

申请日：2008-06-18

申请人： Bang-Thu Nguyen ,  Yan Wang ,  Hong-tsz Pan ,  Xin Wu

发明人： Bang-Thu Nguyen ,  Yan Wang ,  Hong-tsz Pan ,  Xin Wu

IPC分类号： G06F17/50

CPC分类号： G03F1/84

摘要： An integrated circuit device layout and a method for detecting mask data handling errors are disclosed in which integrated circuit device layout includes a device region in which operable circuitry is disposed. Integrated circuit device layout also includes a verification region in which verification elements are disposed. The verification elements include cells that are duplicates of at least some of the different types of cells in device region and can include structures that are duplicates of at least some of the types of structures in the device region. The patterns in verification region are used in the final verification process to identify mask data handling errors in a mask job deck. Because the patterns in verification region are easy to locate and identify, the time required to perform the final verification process is reduced and the chance of error in the final verification process is reduced.

摘要翻译： 公开了一种用于检测掩模数据处理错误的集成电路器件布局和方法，其中集成电路器件布局包括其中设置可操作电路的器件区域。 集成电路装置布局还包括其中设置有验证元件的验证区域。 验证元件包括在设备区域中是至少一些不同类型的单元的重复的单元，并且可以包括在设备区域中至少一些类型的结构的重复的结构。 验证区域中的模式用于最终验证过程，以识别掩模工作台中的掩码数据处理错误。 由于验证区域中的模式易于定位和识别，所以执行最终验证过程所需的时间减少，并且最终验证过程中的错误机会减少。