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    Sensing resistance variable memory
    3.
    发明授权
    Sensing resistance variable memory 有权
    感应电阻变量记忆

    公开(公告)号：US08587984B2

    公开(公告)日：2013-11-19

    申请号：US12847625

    申请日：2010-07-30

    申请人： Pradeep Ramani ,  John D. Porter

    发明人： Pradeep Ramani ,  John D. Porter

    IPC分类号： G11C11/00

    CPC分类号： G11C13/0007 ,  G11C11/5678 ,  G11C11/5685 ,  G11C13/0004 ,  G11C13/0023 ,  G11C13/0028 ,  G11C13/004 ,  G11C13/0061 ,  G11C13/0069 ,  G11C2013/0054 ,  G11C2013/0088 ,  G11C2211/5622 ,  G11C2211/5634 ,  G11C2213/31 ,  G11C2213/32

    摘要： The present disclosure includes devices and methods for operating resistance variable memory. One device embodiment includes an array of memory cells wherein a number of the cells are commonly coupled to a select line, the number cells including a number of data cells programmable within a number of target threshold resistance (Rt) ranges which correspond to a number of data states, and a number of reference cells interleaved with the data cells and programmable within the number of target Rt ranges. The aforementioned device embodiment also includes control circuitry coupled to the array and configured to sense a level associated with at least one data cell and at least one reference cell, and compare the sensed level associated with the at least one data cell with the sensed level associated with the at least one reference cell to determine a data state of the at least one data cell.

    摘要翻译： 本公开包括用于操作电阻变量存储器的装置和方法。 一个设备实施例包括一组存储器单元，其中多个单元共同耦合到选择线，所述数量单元包括在多个目标阈值电阻（Rt）范围内可编程的多个数据单元，其数量对应于 数据状态，以及与数据单元交错并且在目标Rt范围的数目内可编程的多个参考单元。 上述设备实施例还包括耦合到阵列并被配置为感测与至少一个数据单元和至少一个参考单元相关联的电平的控制电路，并且将感测到的与至少一个数据单元相关联的电平与感测电平相关联 与所述至少一个参考单元确定所述至少一个数据单元的数据状态。

    METHODS FOR OPERATING MEMORY ELEMENTS
    4.
    发明申请
    METHODS FOR OPERATING MEMORY ELEMENTS 有权
    操作记忆元素的方法

    公开(公告)号：US20110242878A1

    公开(公告)日：2011-10-06

    申请号：US13159288

    申请日：2011-06-13

    申请人： Jennifer Taylor ,  John D. Porter

    发明人： Jennifer Taylor ,  John D. Porter

    IPC分类号： G11C11/00 ,  G11C7/12

    CPC分类号： G11C13/0004 ,  G11C11/56 ,  G11C11/5678 ,  G11C13/004 ,  G11C27/005 ,  G11C29/50 ,  G11C29/50008 ,  G11C2213/72 ,  G11C2213/79

    摘要： Methods for measuring the resistance of multiple memory elements are disclosed. The memory elements may be multi-bit memory and through precise measurement of resistance of the multi-bit memory elements, determination of how many and which memory elements fall into specific memory ranges can be accomplished. Furthermore, storage and/or display of this information may allow for the creation of resistance distribution histograms for modeling of one or more memory arrays.

    摘要翻译： 公开了用于测量多个存储元件的电阻的方法。 存储器元件可以是多位存储器，并且通过精确测量多位存储器元件的电阻，可以实现多少和哪些存储器元件落入特定存储器范围的确定。 此外，该信息的存储和/或显示可以允许创建用于一个或多个存储器阵列的建模的电阻分布直方图。

    System and method for mitigating reverse bias leakage
    5.
    发明授权
    System and method for mitigating reverse bias leakage 有权
    用于减轻反向偏置泄漏的系统和方法

    公开(公告)号：US08009487B2

    公开(公告)日：2011-08-30

    申请号：US12721290

    申请日：2010-03-10

    申请人： John D. Porter

    发明人： John D. Porter

    IPC分类号： G11C7/10 ,  G11C5/02

    CPC分类号： G11C13/0011 ,  G11C5/025 ,  G11C5/14 ,  G11C7/12 ,  G11C11/5621 ,  G11C13/0004 ,  G11C13/0023 ,  G11C13/0038 ,  G11C13/0069 ,  G11C2213/72 ,  G11C2213/79 ,  Y10T29/49117

    摘要： The present disclosure includes devices, methods, and systems for programming memory, such as resistance variable memory. One embodiment can include an array of resistance variable memory cells, wherein the resistance variable memory cells are coupled to one or more data lines, a row decoder connected to a first side of the array, a column decoder connected to a second side of the array, wherein the second side is adjacent to the first side, a gap located adjacent to the row decoder and the column decoder, and clamp circuitry configured to control a reverse bias voltage associated with one or more unselected memory cells during a programming operation, wherein the clamp circuitry is located in the gap and is selectively coupled to the one or more data lines.

    摘要翻译： 本公开包括用于编程存储器的装置，方法和系统，例如电阻变量存储器。 一个实施例可以包括电阻可变存储单元的阵列，其中电阻可变存储单元耦合到一个或多个数据线，连接到阵列的第一侧的行解码器，连接到阵列第二侧的列解码器 ，其中所述第二侧与所述第一侧相邻，位于所述行解码器和所述列解码器附近的间隙以及被配置为在编程操作期间控制与一个或多个未选择的存储器单元相关联的反向偏置电压的钳位电路，其中， 钳位电路位于间隙中，并且选择性地耦合到一个或多个数据线。

    SENSING RESISTANCE VARIABLE MEMORY
    6.
    发明申请
    SENSING RESISTANCE VARIABLE MEMORY 有权
    感应电阻可变存储器

    公开(公告)号：US20100296331A1

    公开(公告)日：2010-11-25

    申请号：US12847625

    申请日：2010-07-30

    申请人： Pradeep Ramani ,  John D. Porter

    发明人： Pradeep Ramani ,  John D. Porter

    IPC分类号： G11C11/00

    CPC分类号： G11C13/0007 ,  G11C11/5678 ,  G11C11/5685 ,  G11C13/0004 ,  G11C13/0023 ,  G11C13/0028 ,  G11C13/004 ,  G11C13/0061 ,  G11C13/0069 ,  G11C2013/0054 ,  G11C2013/0088 ,  G11C2211/5622 ,  G11C2211/5634 ,  G11C2213/31 ,  G11C2213/32

    摘要： The present disclosure includes devices and methods for operating resistance variable memory. One device embodiment includes an array of memory cells wherein a number of the cells are commonly coupled to a select line, the number cells including a number of data cells programmable within a number of target threshold resistance (Rt) ranges which correspond to a number of data states, and a number of reference cells interleaved with the data cells and programmable within the number of target Rt ranges. The aforementioned device embodiment also includes control circuitry coupled to the array and configured to sense a level associated with at least one data cell and at least one reference cell, and compare the sensed level associated with the at least one data cell with the sensed level associated with the at least one reference cell to determine a data state of the at least one data cell.

    摘要翻译： 本公开包括用于操作电阻变量存储器的装置和方法。 一个设备实施例包括一组存储器单元，其中多个单元共同耦合到选择线，所述数量单元包括在多个目标阈值电阻（Rt）范围内可编程的多个数据单元，其数量对应于 数据状态，以及与数据单元交错并且在目标Rt范围的数目内可编程的多个参考单元。 上述设备实施例还包括耦合到阵列并被配置为感测与至少一个数据单元和至少一个参考单元相关联的电平的控制电路，并且将感测到的与至少一个数据单元相关联的电平与感测电平相关联 与所述至少一个参考单元确定所述至少一个数据单元的数据状态。

    SYSTEM AND METHOD FOR MITIGATING REVERSE BIAS LEAKAGE
    7.
    发明申请
    SYSTEM AND METHOD FOR MITIGATING REVERSE BIAS LEAKAGE 有权
    减轻偏斜泄漏的系统和方法

    公开(公告)号：US20100177574A1

    公开(公告)日：2010-07-15

    申请号：US12721290

    申请日：2010-03-10

    申请人： John D. Porter

    发明人： John D. Porter

    IPC分类号： G11C7/10 ,  H01R43/00 ,  G11C11/00

    CPC分类号： G11C13/0011 ,  G11C5/025 ,  G11C5/14 ,  G11C7/12 ,  G11C11/5621 ,  G11C13/0004 ,  G11C13/0023 ,  G11C13/0038 ,  G11C13/0069 ,  G11C2213/72 ,  G11C2213/79 ,  Y10T29/49117

    摘要： The present disclosure includes devices, methods, and systems for programming memory, such as resistance variable memory. One embodiment can include an array of resistance variable memory cells, wherein the resistance variable memory cells are coupled to one or more data lines, a row decoder connected to a first side of the array, a column decoder connected to a second side of the array, wherein the second side is adjacent to the first side, a gap located adjacent to the row decoder and the column decoder, and clamp circuitry configured to control a reverse bias voltage associated with one or more unselected memory cells during a programming operation, wherein the clamp circuitry is located in the gap and is selectively coupled to the one or more data lines.

    摘要翻译： 本公开包括用于编程存储器的装置，方法和系统，例如电阻变量存储器。 一个实施例可以包括电阻可变存储单元的阵列，其中电阻可变存储单元耦合到一个或多个数据线，连接到阵列的第一侧的行解码器，连接到阵列第二侧的列解码器 ，其中所述第二侧与所述第一侧相邻，位于所述行解码器和所述列解码器附近的间隙以及被配置为在编程操作期间控制与一个或多个未选择的存储器单元相关联的反向偏置电压的钳位电路，其中， 钳位电路位于间隙中，并且选择性地耦合到一个或多个数据线。

    TEMPERATURE COMPENSATION IN MEMORY DEVICES AND SYSTEMS
    8.
    发明申请
    TEMPERATURE COMPENSATION IN MEMORY DEVICES AND SYSTEMS 有权
    存储器件和系统中的温度补偿

    公开(公告)号：US20100067287A1

    公开(公告)日：2010-03-18

    申请号：US12209947

    申请日：2008-09-12

    申请人： John D. Porter ,  Jennifer E. Taylor

    发明人： John D. Porter ,  Jennifer E. Taylor

    IPC分类号： G11C11/00 ,  G11C7/00 ,  G11C17/16

    CPC分类号： G11C17/16 ,  G11C7/04 ,  G11C7/1006 ,  G11C17/18

    摘要： The present disclosure includes devices, methods, and systems for temperature compensation in memory devices, such as resistance variable memory, among other types of memory. One or more embodiments can include a memory device including a table with an output that is used to create a multiplication factor for a current to compensate for temperature changes in the memory device, where the output depends on an operating temperature of the memory device and a difference in the current between a highest specified operating temperature and a lowest specified operating temperature of the memory device.

    摘要翻译： 本公开包括用于存储器件中的温度补偿的装置，方法和系统，诸如电阻变量存储器以及其它类型的存储器。 一个或多个实施例可以包括存储器设备，其包括具有输出的表，该输出用于产生用于补偿存储器件中的温度变化的电流的乘法因子，其中输出取决于存储器件的工作温度和 存储器件的最高规定工作温度和最低规定工作温度之间的电流差。