Copper sputtering target
    1.
    发明授权
    Copper sputtering target 有权
    铜溅射靶

    公开(公告)号:US6149776A

    公开(公告)日:2000-11-21

    申请号:US191253

    申请日:1998-11-12

    IPC分类号: C23C14/34 H01J37/34

    CPC分类号: H01J37/3435 C23C14/3407

    摘要: The present invention generally provides an apparatus and a method for physical vapor deposition of a metal onto a substrate comprising a physical vapor deposition chamber and a target disposed in an upper portion of the chamber. The target comprises a backing plate having a central portion and a flange portion attachable to the physical vapor deposition chamber, a sputterable portion extending from the central portion of the backing plate, and an annular ridge disposed on a surface of the flange portion. Preferably, the sputterable portion of the target includes a restriction side wall that restricts entry of plasma and back-scattered particles into the dark space gap between an upper shield and the target.

    摘要翻译: 本发明通常提供一种将金属物理气相沉积到衬底上的装置和方法,该衬底包括物理气相沉积室和设置在腔室上部的靶。 目标包括具有中心部分和可连接到物理气相沉积室的凸缘部分的背板,从背板的中心部分延伸的可溅射部分和设置在凸缘部分的表面上的环形凸脊。 优选地,靶的可溅射部分包括限制侧壁,其限制等离子体和背散射粒子进入上屏蔽和靶之间的暗空间间隙。

    Copper alloy seed layer for copper metallization
    2.
    发明授权
    Copper alloy seed layer for copper metallization 失效
    铜合金种子层用于铜金属化

    公开(公告)号:US06387805B2

    公开(公告)日:2002-05-14

    申请号:US08878143

    申请日:1997-06-18

    IPC分类号: H01L2144

    摘要: A copper metallization structure and its method of formation in which a layer of a copper alloy, such as Cu—Mg or Cu—Al is deposited over a silicon oxide based dielectric layer and a substantially pure copper layer is deposited over the copper alloy layer. The copper alloy layer serves as a seed or wetting layer for subsequent filling of via holes and trenches with substantially pure copper. Preferably, the copper alloy is deposited cold in a sputter process, but, during the deposition of the pure copper layer or afterwards in a separate annealing step, the temperature is raised sufficiently high to cause the alloying element of the copper alloy to migrate to the dielectric layer and form a barrier there against diffusion of copper into and through the dielectric layer. This barrier also promotes adhesion of the alloy layer to the dielectric layer, thereby forming a superior wetting and seed layer for subsequent copper full-fill techniques. Filling of the alloy-lined feature can be accomplished using PVD, CVD, or electro/electroless plating.

    摘要翻译: 在铜合金层上沉积铜基金属化结构及其形成方法,其中在氧化硅基介电层和基本上纯的铜层上沉积诸如Cu-Mg或Cu-Al的铜合金层。 铜合金层用作种子或润湿层,用于随后用基本上纯的铜填充通孔和沟槽。 优选地,铜合金在溅射过程中冷沉积,但是在纯铜层沉积期间或之后在单独的退火步骤中,温度升高到足够高以使铜合金的合金元素迁移到 电介质层,并形成阻挡铜,以扩散到介电层中并穿过介电层。 该屏障还促进了合金层对电介质层的粘附,从而形成了用于随后的铜全填充技术的优异的润湿和种子层。 可以使用PVD,CVD或电/无电镀来完成合金衬里特征的填充。

    Structure for improving low temperature copper reflow in semiconductor features
    3.
    发明授权
    Structure for improving low temperature copper reflow in semiconductor features 失效
    用于改善半导体特性中低温铜回流的结构

    公开(公告)号:US06352926B1

    公开(公告)日:2002-03-05

    申请号:US09709991

    申请日:2000-11-10

    IPC分类号: H01L2144

    摘要: We have discovered that complete copper filling of semiconductor features such as trenches and vias, without the formation of trapped voids, can be accomplished using a copper reflow process when the unfilled portion of the feature structure prior to reflow comprises a capillary within the feature, wherein the volume of the capillary represents between about 20% and about 90%, preferably between about 20% and about 75% of the original feature volume prior to filling with copper. The aspect ratio of the capillary is preferably at least 1.5. The maximum opening dimension of the capillary is less than about 0.8 &mgr;m. The preferred substrate temperature during the reflow process includes either a soak at an individual temperature or a temperature ramp-up or ramp-down where the substrate experiences a temperature within a range from about 300° C. to about 600° C., more preferably between about 300° C. and about 450° C. By controlling the percentage of the volume of the feature which is unfilled at the time of the reflow process and taking advantage of the surface tension and capillary action when the aspect ratio of the feature is at least 1.5, the copper fill material is easily pulled into the feature which comprises the capillary without the formation of voids along the walls of the feature. The preferred method of application of the last layer of copper prior to reflow (the layer of copper which produces the unfilled capillary within the feature) is electroplating, although CVD or evaporation or other conformal layer formation techniques may be used.

    摘要翻译: 我们已经发现,当回流焊之前的特征结构的未填充部分包括该特征内的毛细管时,可以使用铜回流工艺来实现半导体特征如沟槽和通孔的完全铜填充,例如沟槽和通孔,而不形成截留的空隙,其中 在填充铜之前,毛细管的体积代表原始特征体积的约20%至约90%,优选约20%至约75%。 毛细管的纵横比优选为1.5以上。 毛细管的最大开口尺寸小于约0.8μm。 在回流过程中优选的衬底温度包括在单独温度下浸泡或温度升高或斜坡下降,其中衬底经历温度在约300℃至约600℃的范围内,更优选地 在约300℃和约450℃之间。通过控制在回流工艺时未填充的特征的体积百分比,并且当特征的纵横比为 至少1.5,铜填充材料容易地被拉入包括毛细管的特征,而不沿着特征的壁形成空隙。 在回流之前施加最后一层铜的优选方法(在特征内产生未填充的毛细管的铜层)是电镀,尽管可以使用CVD或蒸发或其它共形层形成技术。

    Copper alloy seed layer for copper metallization in an integrated circuit
    6.
    发明授权
    Copper alloy seed layer for copper metallization in an integrated circuit 失效
    铜合金种子层用于集成电路中的铜金属化

    公开(公告)号:US06066892A

    公开(公告)日:2000-05-23

    申请号:US79107

    申请日:1998-05-14

    摘要: A copper metallization structure in which a layer of a copper alloy, such as Cu--Mg or Cu--Al is deposited over a silicon oxide based dielectric layer and a substantially pure copper layer is deposited over the copper alloy layer. The copper alloy layer serves as a seed or wetting layer for subsequent filling of via holes and trenches with substantially pure copper. Preferred examples of the alloying elements and their atomic alloying percentage include magnesium between 0.05 and 6% and aluminum between 0.05 and 0.3%. Further examples include boron, tantalum, tellurium, and titanium. Preferably, the copper alloy is deposited cold in a sputter process, but, during the deposition of the pure copper layer or afterwards in a separate annealing step, the temperature is raised sufficiently high to cause the alloying element of the copper alloy to migrate to the dielectric layer and form a barrier there against diffusion of copper into and through the dielectric layer. This barrier also promotes adhesion of the alloy layer to the dielectric layer, thereby forming a superior wetting and seed layer for subsequent copper full-fill techniques. Filling of the alloy-lined feature can be accomplished using PVD, CVD, or electro/electroless plating.

    摘要翻译: 在铜合金层上沉积铜基金属化结构,其中在氧化硅基介电层和基本上纯的铜层上沉积诸如Cu-Mg或Cu-Al的铜合金层。 铜合金层用作种子或润湿层,用于随后用基本上纯的铜填充通孔和沟槽。 合金元素的优选实例及其原子合金化百分比包括0.05至6%的镁和0.05-0.3%的铝。 其他实例包括硼,钽,碲和钛。 优选地,铜合金在溅射过程中冷沉积,但是在纯铜层沉积期间或之后在单独的退火步骤中,温度升高到足够高以使铜合金的合金元素迁移到 电介质层,并形成阻挡铜,以扩散到介电层中并穿过介电层。 该屏障还促进了合金层对电介质层的粘附,从而形成了用于随后的铜全填充技术的优异的润湿和种子层。 可以使用PVD,CVD或电/无电镀来完成合金衬里特征的填充。

    Copper alloy via structure
    8.
    发明授权
    Copper alloy via structure 有权
    铜合金通孔结构

    公开(公告)号:US6160315A

    公开(公告)日:2000-12-12

    申请号:US478721

    申请日:2000-01-06

    摘要: A copper via structure formed when copper and a small amount of an alloying metal such as magnesium or aluminum are cosputtered onto a substrate having oxide on at least a portion of its surface. Either the wafer is held at an elevated temperature during deposition or the sputtered film is annealed without the wafer being exposed to ambient. Due to the high temperature, the alloying metal diffuses to the surface. If a surface is exposed to a low partial pressure of oxygen or contacts silicon dioxide, the magnesium or aluminum forms a thin stable oxide but also extends into the oxide a distance of about 100 nm. The alloying metal oxide having a thickness of about 6 nm on the oxide sidewalls encapsulates the copper layer to provide a barrier against copper migration, to form an adhesion layer over silicon dioxide, and to act as a seed layer for the later growth of copper, for example, by electroplating.

    摘要翻译: 当铜和少量的合金金属如镁或铝形成的铜通孔结构在其表面的至少一部分上被分散在具有氧化物的基底上。 在沉积期间晶片保持在升高的温度下,或者溅射膜被退火而晶片不暴露于环境中。 由于高温,合金金属扩散到表面。 如果表面暴露于低的氧分压或接触二氧化硅,则镁或铝形成薄的稳定氧化物,但也延伸到氧化物中约100nm的距离。 在氧化物侧壁上具有约6nm厚度的合金化金属氧化物封装铜层以提供阻挡铜迁移的屏障,以形成二氧化硅以上的粘合层,并且用作后续生长铜的种子层, 例如,通过电镀。

    Method for achieving copper fill of high aspect ratio interconnect features
    10.
    发明授权
    Method for achieving copper fill of high aspect ratio interconnect features 有权
    实现高宽比互连特征铜填充的方法

    公开(公告)号:US06436267B1

    公开(公告)日:2002-08-20

    申请号:US09650108

    申请日:2000-08-29

    IPC分类号: C23C2802

    CPC分类号: H01L21/2885 H01L21/76877

    摘要: One aspect of the invention provides a consistent metal electroplating technique to form void-less metal interconnects in sub-micron high aspect ratio features on semiconductor substrates. One embodiment of the invention provides a method for filling sub-micron features on a substrate, comprising reactive precleaning the substrate, depositing a barrier layer on the substrate using high density plasma physical vapor deposition; depositing a seed layer over the barrier layer using high density plasma physical vapor deposition; and electro-chemically depositing a metal using a highly resistive electrolyte and applying a first current density during a first deposition period followed by a second current density during a second period.

    摘要翻译: 本发明的一个方面提供一致的金属电镀技术,以在半导体衬底上形成亚微米高纵横比特征的无空隙金属互连。 本发明的一个实施方案提供了一种用于在基底上填充亚微米特征的方法,包括反应性预清洗基底,使用高密度等离子体物理气相沉积在基底上沉积阻挡层; 使用高密度等离子体物理气相沉积在阻挡层上沉积种子层; 以及使用高电阻电解质电化学沉积金属,并且在第一周期期间在第一沉积期间施加第一电流密度,然后施加第二电流密度。