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    Copper alloy seed layer for copper metallization
    1.
    发明授权
    Copper alloy seed layer for copper metallization 失效
    铜合金种子层用于铜金属化

    公开(公告)号：US06387805B2

    公开(公告)日：2002-05-14

    申请号：US08878143

    申请日：1997-06-18

    申请人： Peijun Ding ,  Tony Chiang ,  Imran Hashim ,  Bingxi Sun ,  Barry Chin

    发明人： Peijun Ding ,  Tony Chiang ,  Imran Hashim ,  Bingxi Sun ,  Barry Chin

    IPC分类号： H01L2144

    CPC分类号： H01L21/76843 ,  C23C14/024 ,  C23C14/025 ,  C23C14/16 ,  C23C14/165 ,  C23C16/0281 ,  C23C16/06 ,  H01L21/2855 ,  H01L21/28556 ,  H01L21/76831 ,  H01L21/76834 ,  H01L21/76867 ,  H01L21/76871 ,  H01L21/76877 ,  H01L21/76888 ,  H01L23/53233 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A copper metallization structure and its method of formation in which a layer of a copper alloy, such as Cu—Mg or Cu—Al is deposited over a silicon oxide based dielectric layer and a substantially pure copper layer is deposited over the copper alloy layer. The copper alloy layer serves as a seed or wetting layer for subsequent filling of via holes and trenches with substantially pure copper. Preferably, the copper alloy is deposited cold in a sputter process, but, during the deposition of the pure copper layer or afterwards in a separate annealing step, the temperature is raised sufficiently high to cause the alloying element of the copper alloy to migrate to the dielectric layer and form a barrier there against diffusion of copper into and through the dielectric layer. This barrier also promotes adhesion of the alloy layer to the dielectric layer, thereby forming a superior wetting and seed layer for subsequent copper full-fill techniques. Filling of the alloy-lined feature can be accomplished using PVD, CVD, or electro/electroless plating.

    摘要翻译： 在铜合金层上沉积铜基金属化结构及其形成方法，其中在氧化硅基介电层和基本上纯的铜层上沉积诸如Cu-Mg或Cu-Al的铜合金层。 铜合金层用作种子或润湿层，用于随后用基本上纯的铜填充通孔和沟槽。 优选地，铜合金在溅射过程中冷沉积，但是在纯铜层沉积期间或之后在单独的退火步骤中，温度升高到足够高以使铜合金的合金元素迁移到 电介质层，并形成阻挡铜，以扩散到介电层中并穿过介电层。 该屏障还促进了合金层对电介质层的粘附，从而形成了用于随后的铜全填充技术的优异的润湿和种子层。 可以使用PVD，CVD或电/无电镀来完成合金衬里特征的填充。

    Copper alloy via structure
    2.
    发明授权
    Copper alloy via structure 有权
    铜合金通孔结构

    公开(公告)号：US6160315A

    公开(公告)日：2000-12-12

    申请号：US478721

    申请日：2000-01-06

    申请人： Tony Chiang ,  Peijun Ding ,  Barry Chin ,  Imran Hashim ,  Bingxi Sun

    发明人： Tony Chiang ,  Peijun Ding ,  Barry Chin ,  Imran Hashim ,  Bingxi Sun

    IPC分类号： C23C14/02 ,  C23C14/16 ,  C23C16/02 ,  C23C16/06 ,  H01L21/285 ,  H01L21/768 ,  H01L23/532 ,  H01L23/48

    CPC分类号： H01L21/76834 ,  C23C14/024 ,  C23C14/025 ,  C23C14/16 ,  C23C14/165 ,  C23C16/0281 ,  C23C16/06 ,  H01L21/2855 ,  H01L21/76831 ,  H01L21/76843 ,  H01L21/76871 ,  H01L21/76877 ,  H01L21/76888 ,  H01L23/53233 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A copper via structure formed when copper and a small amount of an alloying metal such as magnesium or aluminum are cosputtered onto a substrate having oxide on at least a portion of its surface. Either the wafer is held at an elevated temperature during deposition or the sputtered film is annealed without the wafer being exposed to ambient. Due to the high temperature, the alloying metal diffuses to the surface. If a surface is exposed to a low partial pressure of oxygen or contacts silicon dioxide, the magnesium or aluminum forms a thin stable oxide but also extends into the oxide a distance of about 100 nm. The alloying metal oxide having a thickness of about 6 nm on the oxide sidewalls encapsulates the copper layer to provide a barrier against copper migration, to form an adhesion layer over silicon dioxide, and to act as a seed layer for the later growth of copper, for example, by electroplating.

    摘要翻译： 当铜和少量的合金金属如镁或铝形成的铜通孔结构在其表面的至少一部分上被分散在具有氧化物的基底上。 在沉积期间晶片保持在升高的温度下，或者溅射膜被退火而晶片不暴露于环境中。 由于高温，合金金属扩散到表面。 如果表面暴露于低的氧分压或接触二氧化硅，则镁或铝形成薄的稳定氧化物，但也延伸到氧化物中约100nm的距离。 在氧化物侧壁上具有约6nm厚度的合金化金属氧化物封装铜层以提供阻挡铜迁移的屏障，以形成二氧化硅以上的粘合层，并且用作后续生长铜的种子层， 例如，通过电镀。

    Copper alloy seed layer for copper metallization in an integrated circuit
    3.
    发明授权
    Copper alloy seed layer for copper metallization in an integrated circuit 失效
    铜合金种子层用于集成电路中的铜金属化

    公开(公告)号：US06066892A

    公开(公告)日：2000-05-23

    申请号：US79107

    申请日：1998-05-14

    申请人： Peijun Ding ,  Tony Chiang ,  Imran Hashim ,  Bingxi Sun ,  Barry Chin

    发明人： Peijun Ding ,  Tony Chiang ,  Imran Hashim ,  Bingxi Sun ,  Barry Chin

    IPC分类号： H01L21/28 ,  C23C14/02 ,  C23C14/16 ,  C23C16/02 ,  C23C16/06 ,  H01L21/203 ,  H01L21/285 ,  H01L21/3205 ,  H01L21/768 ,  H01L23/52 ,  H01L23/532 ,  H01L29/45

    CPC分类号： H01L21/76843 ,  C23C14/024 ,  C23C14/025 ,  C23C14/16 ,  C23C14/165 ,  C23C16/0281 ,  C23C16/06 ,  H01L21/28556 ,  H01L21/76831 ,  H01L21/76834 ,  H01L21/76867 ,  H01L21/76871 ,  H01L21/76877 ,  H01L21/76888 ,  H01L23/53233 ,  H01L23/53238 ,  H01L21/2855 ,  H01L2924/0002

    摘要： A copper metallization structure in which a layer of a copper alloy, such as Cu--Mg or Cu--Al is deposited over a silicon oxide based dielectric layer and a substantially pure copper layer is deposited over the copper alloy layer. The copper alloy layer serves as a seed or wetting layer for subsequent filling of via holes and trenches with substantially pure copper. Preferred examples of the alloying elements and their atomic alloying percentage include magnesium between 0.05 and 6% and aluminum between 0.05 and 0.3%. Further examples include boron, tantalum, tellurium, and titanium. Preferably, the copper alloy is deposited cold in a sputter process, but, during the deposition of the pure copper layer or afterwards in a separate annealing step, the temperature is raised sufficiently high to cause the alloying element of the copper alloy to migrate to the dielectric layer and form a barrier there against diffusion of copper into and through the dielectric layer. This barrier also promotes adhesion of the alloy layer to the dielectric layer, thereby forming a superior wetting and seed layer for subsequent copper full-fill techniques. Filling of the alloy-lined feature can be accomplished using PVD, CVD, or electro/electroless plating.

    摘要翻译： 在铜合金层上沉积铜基金属化结构，其中在氧化硅基介电层和基本上纯的铜层上沉积诸如Cu-Mg或Cu-Al的铜合金层。 铜合金层用作种子或润湿层，用于随后用基本上纯的铜填充通孔和沟槽。 合金元素的优选实例及其原子合金化百分比包括0.05至6％的镁和0.05-0.3％的铝。 其他实例包括硼，钽，碲和钛。 优选地，铜合金在溅射过程中冷沉积，但是在纯铜层沉积期间或之后在单独的退火步骤中，温度升高到足够高以使铜合金的合金元素迁移到 电介质层，并形成阻挡铜，以扩散到介电层中并穿过介电层。 该屏障还促进了合金层对电介质层的粘附，从而形成了用于随后的铜全填充技术的优异的润湿和种子层。 可以使用PVD，CVD或电/无电镀来完成合金衬里特征的填充。

    Method for achieving copper fill of high aspect ratio interconnect features
    8.
    发明授权
    Method for achieving copper fill of high aspect ratio interconnect features 有权
    实现高宽比互连特征铜填充的方法

    公开(公告)号：US06436267B1

    公开(公告)日：2002-08-20

    申请号：US09650108

    申请日：2000-08-29

    申请人： Daniel A. Carl ,  Barry Chin ,  Liang Chen ,  Robin Cheung ,  Peijun Ding ,  Yezdi Dordi ,  Imran Hashim ,  Peter Hey ,  Ashok K. Sinha

    发明人： Daniel A. Carl ,  Barry Chin ,  Liang Chen ,  Robin Cheung ,  Peijun Ding ,  Yezdi Dordi ,  Imran Hashim ,  Peter Hey ,  Ashok K. Sinha

    IPC分类号： C23C2802

    CPC分类号： H01L21/2885 ,  H01L21/76877

    摘要： One aspect of the invention provides a consistent metal electroplating technique to form void-less metal interconnects in sub-micron high aspect ratio features on semiconductor substrates. One embodiment of the invention provides a method for filling sub-micron features on a substrate, comprising reactive precleaning the substrate, depositing a barrier layer on the substrate using high density plasma physical vapor deposition; depositing a seed layer over the barrier layer using high density plasma physical vapor deposition; and electro-chemically depositing a metal using a highly resistive electrolyte and applying a first current density during a first deposition period followed by a second current density during a second period.

    摘要翻译： 本发明的一个方面提供一致的金属电镀技术，以在半导体衬底上形成亚微米高纵横比特征的无空隙金属互连。 本发明的一个实施方案提供了一种用于在基底上填充亚微米特征的方法，包括反应性预清洗基底，使用高密度等离子体物理气相沉积在基底上沉积阻挡层; 使用高密度等离子体物理气相沉积在阻挡层上沉积种子层; 以及使用高电阻电解质电化学沉积金属，并且在第一周期期间在第一沉积期间施加第一电流密度，然后施加第二电流密度。

    Method and apparatus for forming improved metal interconnects
    9.
    发明授权
    Method and apparatus for forming improved metal interconnects 失效
    用于形成改进的金属互连的方法和装置

    公开(公告)号：US06287977B1

    公开(公告)日：2001-09-11

    申请号：US09126890

    申请日：1998-07-31

    申请人： Imran Hashim ,  Tony Chiang ,  Barry Chin

    发明人： Imran Hashim ,  Tony Chiang ,  Barry Chin

    IPC分类号： H01L21302

    CPC分类号： H01L21/76844 ,  H01L21/76805 ,  H01L21/76814 ,  H01L21/76831 ,  H01L21/76834 ,  H01L21/76838 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

    摘要： Methods of forming copper interconnects free from via-to-via leakage currents and having low resistances are disclosed. In a first aspect, a barrier layer is deposited on the first metal layer prior to copper oxide sputter-etching to prevent copper atoms from reaching the interlayer dielectric and forming via-to-via leakage current paths therein. In a second aspect, a capping dielectric barrier layer is deposited over the first metal layer prior to sputter etching. During sputter-etching, the capping dielectric barrier layer redistributes on the sidewalls of the interlayer dielectric, preventing sputter-etched copper atoms from reaching the interlayer dielectric and forming via-to-via leakage paths therein. In a third aspect, both a capping dielectric barrier layer and a barrier layer are deposited over the first metal layer prior to sputter-etching to prevent copper atoms produced during sputter-etching from reaching the interlayer dielectric and forming via-to-via leakage paths therein.

    摘要翻译： 公开了形成没有通孔到通孔泄漏电流并具有低电阻的铜互连的方法。 在第一方面，在铜氧化物溅射蚀刻之前，在第一金属层上沉积阻挡层，以防止铜原子到达层间电介质，并在其中形成通孔到漏电流路径。 在第二方面，在溅射蚀刻之前，在第一金属层上沉积封盖电介质阻挡层。 在溅射蚀刻期间，封盖电介质阻挡层重新分布在层间电介质的侧壁上，防止溅射蚀刻的铜原子到达层间电介质并在其中形成通孔到通孔泄漏路径。 在第三方面，在溅射蚀刻之前，在第一金属层上沉积封盖介电阻挡层和阻挡层，以防止在溅射蚀刻期间产生的铜原子到达层间电介质并形成通孔到通孔泄漏路径 其中。

    Method and apparatus for forming improved metal interconnects
    10.
    发明授权
    Method and apparatus for forming improved metal interconnects 失效

    公开(公告)号：US06559061B2

    公开(公告)日：2003-05-06

    申请号：US09928891

    申请日：2001-08-13

    申请人： Imran Hashim ,  Tony Chiang ,  Barry Chin

    发明人： Imran Hashim ,  Tony Chiang ,  Barry Chin

    IPC分类号： H01L21302

    CPC分类号： H01L21/76844 ,  H01L21/76805 ,  H01L21/76814 ,  H01L21/76831 ,  H01L21/76834 ,  H01L21/76838 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

    摘要： Methods of forming copper interconnects free from via-to-via leakage currents and having low resistances are disclosed. In a first aspect, a barrier layer is deposited on the first metal layer prior to copper oxide sputter-etching to prevent copper atoms from reaching the interlayer dielectric and forming via-to-via leakage current paths therein. In a second aspect, a capping dielectric barrier layer is deposited over the first metal layer prior to sputter etching. During sputter-etching, the capping dielectric barrier layer redistributes on the sidewalls of the interlayer dielectric, preventing sputter-etched copper atoms from reaching the interlayer dielectric and forming via-to-via leakage paths therein. In a third aspect, both a capping dielectric barrier layer and a barrier layer are deposited over the first metal layer prior to sputter-etching to prevent copper atoms produced during sputter-etching from reaching the interlayer dielectric and forming via-to-via leakage paths therein.