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12 条记录 (耗时 0.035 秒)

    Automatic hardware message header generator
    2.
    发明授权
    Automatic hardware message header generator 失效
    自动硬件消息头生成器

    公开(公告)号：US5922063A

    公开(公告)日：1999-07-13

    申请号：US946509

    申请日：1992-09-17

    申请人： Howard Thomas Olnowich ,  Michael Wayland Dotson ,  James William Feeney ,  Robert Francis Lusch ,  Michael Anthony Maniguet

    发明人： Howard Thomas Olnowich ,  Michael Wayland Dotson ,  James William Feeney ,  Robert Francis Lusch ,  Michael Anthony Maniguet

    IPC分类号： G06F13/00 ,  G06F15/173

    CPC分类号： G06F15/17375

    摘要： A method and apparatus for reducing the software overhead of message passing in parallel systems. Special purpose hardware assists in constructing each data message sent through a network. Message passing systems generally require that every message be prefixed with a message header describing the key control parameters of the message. The software task is to construct the message header for every message individually and to transmit the header prefixed to every message. The software is relieved of constructing the message header and uses special purpose hardware to accomplish the job more efficiently.

    摘要翻译： 一种用于减少并行系统中消息传递的软件开销的方法和装置。 专用硬件有助于构建通过网络发送的每个数据消息。 消息传递系统通常要求每个消息都带有描述消息的密钥控制参数的消息头。 软件任务是单独构建每个消息的消息头，并将标题发送到每个消息。 该软件不需要构建消息头，并且使用专用硬件来更有效地完成工作。

    Selectable checking of message destinations in a switched parallel network
    4.
    发明授权
    Selectable checking of message destinations in a switched parallel network 失效
    可选择检查交换并行网络中的消息目的地

    公开(公告)号：US5786771A

    公开(公告)日：1998-07-28

    申请号：US17088

    申请日：1993-02-12

    申请人： James William Feeney ,  John David Jabusch ,  Robert Francis Lusch ,  Howard Thomas Olnowich

    发明人： James William Feeney ,  John David Jabusch ,  Robert Francis Lusch ,  Howard Thomas Olnowich

    IPC分类号： G06F13/00 ,  G06F15/173 ,  H04L12/18 ,  H04L12/56 ,  H04Q1/00

    CPC分类号： H04L12/1877 ,  H04L45/00

    摘要： A method and hardware apparatus provide a fault tolerant and flexible multi-stage network addressing scheme for transmitting a message with a header containing control bits for selecting from various destination checking functions to be performed. Upon arrival of the message at a node, destination checking is performed or not in response to the massage's header. If destination checking is not performed, or if destination checking is performed and indicates that the node is the desired destination for the message, the message is accepted. If destination checking is performed and indicates that the node is not the desired destination for the message, the message is rejected. Destination checking is disabled during address assignment, broadcasting and multi-casting, and replaced with one's complement-based verification of the sending node.

    摘要翻译： 方法和硬件设备提供容错和灵活的多级网络寻址方案，用于发送具有包含用于从要执行的各种目的地检查功能进行选择的控制位的报头的消息。 在消息到达节点时，响应于按摩头部执行目的地检查。 如果未执行目的地检查，或者执行目的地检查并指示节点是消息的所需目的地，则接受该消息。 如果执行了目的地检查，并指示该节点不是该消息的所需目的地，则该消息被拒绝。 在地址分配，广播和多播期间禁用目的地检查，并替换为发送节点的补码验证。

    Method and apparatus for maintaining message order in multi-user FIFO stacks
    5.
    发明授权
    Method and apparatus for maintaining message order in multi-user FIFO stacks 失效
    用于在多用户FIFO堆栈中维护消息顺序的方法和装置

    公开(公告)号：US5901291A

    公开(公告)日：1999-05-04

    申请号：US731809

    申请日：1996-10-21

    申请人： James William Feeney ,  Howard Thomas Olnowich ,  George William Wilhelm, Jr.

    发明人： James William Feeney ,  Howard Thomas Olnowich ,  George William Wilhelm, Jr.

    IPC分类号： G06F13/12 ,  H04L12/56 ,  G06F13/00

    CPC分类号： H04L49/9073 ,  G06F13/128 ,  H04L49/90 ,  H04L49/901 ,  H04L49/9031

    摘要： A digital parallel processing system wherein a plurality of nodes communicate via messages sent over an interconnection network. Messages are maintained in strict chronological order even though sent by nodes where several sources are generating messages simultaneously. A network adapter is described for interconnecting the processor and its associated memory to a network over a bus. The adapter includes an adapter associated memory programmable into a plurality of functional areas, said functional areas including a send FIFO for storing and forwarding messages to said network from said processor; a stack list for queueing in strict message order activation commands for said send FIFO; and an adapter program area for storing adapter program instructions which control the storing of messages to said send FIFO; and control means responsive to said stack list for executing said adapter program instructions in said strict message order without processor intervention.

    摘要翻译： 一种数字并行处理系统，其中多个节点通过互连网络发送的消息进行通信。 即使由多个源同时生成消息的节点发送，消息也将以严格的时间顺序进行维护。 描述了一种网络适配器，用于通过总线将处理器及其相关联的存储器互连到网络。 适配器包括可编程到多个功能区域中的适配器相关联的存储器，所述功能区域包括用于从所述处理器存储和转发消息到所述网络的发送FIFO; 用于排队所述发送FIFO的严格消息顺序激活命令的堆栈列表; 以及适配器程序区域，用于存储控制向所述发送FIFO存储消息的适配器程序指令; 以及响应所述堆栈列表的控制装置，用于在没有处理器干预的情况下以所述严格消息顺序执行所述适配器程序指令

    Multi-tasking adapter for parallel network applications
    6.
    发明授权
    Multi-tasking adapter for parallel network applications 失效
    用于并行网络应用的多任务适配器

    公开(公告)号：US06408341B1

    公开(公告)日：2002-06-18

    申请号：US09496736

    申请日：2000-02-02

    申请人： James William Feeney ,  Howard Thomas Olnowich ,  George William Wilhelm, Jr.

    发明人： James William Feeney ,  Howard Thomas Olnowich ,  George William Wilhelm, Jr.

    IPC分类号： G06F900

    CPC分类号： G06F9/544

    摘要： A communications apparatus is provided comprising a plurality of FIFO buffers, each with independent control and priority logic under software control for supporting different types of message traffic, both send and receive, such as comprise a multimedia server system. Processor software directs messages to specific, optimized FIFO buffers. Further, a system is provided including a plurality of nodes wherein a sending node specifies the communications path through the system, selecting specific FIFO buffers in each node for buffering its messages.

    摘要翻译： 提供一种通信装置，其包括多个FIFO缓冲器，每个FIFO缓冲器具有软件控制下的独立控制和优先级逻辑，用于支持诸如包括多媒体服务器系统的发送和接收的不同类型的消息业务。 处理器软件将消息指向特定的优化FIFO缓冲区。 此外，提供了包括多个节点的系统，其中发送节点指定通过系统的通信路径，在每个节点中选择用于缓冲其消息的特定FIFO缓冲器。

    Increasing probability multi-stage network
    7.
    发明授权
    Increasing probability multi-stage network 失效
    增加概率多级网络

    公开(公告)号：US06226683B1

    公开(公告)日：2001-05-01

    申请号：US08625379

    申请日：1996-04-01

    申请人： Howard Thomas Olnowich ,  Jehoshua Bruck ,  James William Feeney ,  Eli Upfal

    发明人： Howard Thomas Olnowich ,  Jehoshua Bruck ,  James William Feeney ,  Eli Upfal

    IPC分类号： G06F15173

    CPC分类号： H04Q3/685 ,  H04J2203/0012 ,  H04Q11/0478 ,  H04Q2213/13322 ,  H04Q2213/1334

    摘要： Disclosed is is a switch-based network interconnection which uses intelligent switching apparatus devices for improving the performance and connection establishing capability of multi-stage switching networks. The invention method is particularly effective In asynchronous circuit-switched networks. The most important feature of the invention methodology is the an increasing probability for the success of making a connection through all the stages of a multi-satge network. As a connection progresses through a multi-stage network, it must win successive stages of the network, one at a time, until it has made its way from on side of the network to the other and established the commanded source-to-destination connection. The uniqueness in the present invention is that as the connection at each stage of the network is established, looking forward to the next stage, the probability will be greater of establishing the next connection without encountering blocking than it was for the present stage. This presents an ever increasing probability for establishing a successful connection as a path works its way through the network. This is opposite of most traditional networks, whose probabiltiy for success diminishes with every stage in the connection sequence.

    摘要翻译： 公开了一种基于交换机的网络互连，其使用智能交换设备装置来提高多级交换网络的性能和连接建立能力。 本发明方法在异步电路交换网络中特别有效。 本发明方法的最重要的特征是通过多平台网络的所有阶段进行连接成功的可能性越来越大。 由于通过多阶段网络进行连接，它必须一次赢得网络的连续阶段，直到从网络侧到另一侧网络建立起命令的源到目的地连接 。 本发明的唯一性在于，当网络的每个阶段的连接建立时，期待下一个阶段，建立下一个连接的可能性将大于当前阶段不会遇到阻塞的概率。 随着路径在网络中的运行，这种建立成功连接的可能性越来越大。 这与大多数传统网络相反，传统网络的成功可能性在连接顺序的每个阶段都会减少。

    Multi-stage interconnection network with selectable function switching apparatus
    8.
    发明授权
    Multi-stage interconnection network with selectable function switching apparatus 失效
    具有可选功能开关装置的多级互联网络

    公开(公告)号：US5835024A

    公开(公告)日：1998-11-10

    申请号：US481855

    申请日：1995-06-07

    申请人： Howard Thomas Olnowich ,  Jehoshua Bruck ,  James William Feeney ,  Michael Hans Fisher ,  Eliezer Upfal ,  Arthur Robert Williams

    发明人： Howard Thomas Olnowich ,  Jehoshua Bruck ,  James William Feeney ,  Michael Hans Fisher ,  Eliezer Upfal ,  Arthur Robert Williams

    IPC分类号： G06F15/173 ,  H03K17/04

    CPC分类号： G06F15/17393

    摘要： The present invention addresses the limitations of prior art ALLNODE switches by including dual priority, adaptive, path seeking, and flash-flood functionalities in a single ALLNODE switch. The switch of the present invention further includes a selection device responsive to a selection signal for enabling the selection of the mode of switch operation from any one of the foregoing functionalities. The selection signal is applied to the switch in a number of different ways including: the transmission of a command over the data path interface to the switch; the transmission of a command over special purpose serial or parallel control lines; or via hardwiring. Thus, the selection of functionality for the switch is capable of being made in either a dynamic or static fashion. The present invention further comprises two new high performance networks utilizing the selectable function ALLNODE switch. The networks have a different functionality being performed at each stage, and comprise a "Multi-Dilated Path Seeking Network" and a "Nested Path Seeking and Flash-Flood Network."

    摘要翻译： 本发明通过在单个ALLNODE交换机中包括双重优先级，自适应，寻路和闪存功能来解决现有技术的ALLNODE交换机的局限性。 本发明的开关还包括响应于选择信号的选择装置，用于使得能够从前述功能中的任一个选择开关操作模式。 选择信号以多种不同的方式应用于交换机，包括：通过数据路径接口向交换机发送命令; 通过专用串行或并行控制线传输命令; 或通过硬连线。 因此，切换器的功能的选择能够以动态或静态方式进行。 本发明还包括利用可选功能ALLNODE开关的两个新的高性能网络。 网络具有在每个阶段执行的不同功能，并且包括“多扩展路径寻求网络”和“嵌套路径寻求和闪存洪泛网络”。

    Low power access to a computing unit from an external source
    10.
    发明授权
    Low power access to a computing unit from an external source 失效
    从外部来源对计算单元进行低功耗访问

    公开(公告)号：US06922788B2

    公开(公告)日：2005-07-26

    申请号：US09955821

    申请日：2001-09-19

    申请人： Raymond J. Eberhard ,  James William Feeney

    发明人： Raymond J. Eberhard ,  James William Feeney

    IPC分类号： G06F1/32

    CPC分类号： G06F1/3287 ,  G06F1/3203 ,  G06F1/3209 ,  Y02D10/171 ,  Y02D50/20

    摘要： A method for conserving energy in a computing unit and transferring data between the computing unit and an external source. The computing unit is in a power saving mode. The method includes receiving at the computing unit a request from an external source, determining which components of the computing unit are required to respond to the request, selectively activating, from the power saving mode, the components of the computing unit necessary to respond the request, and responding to the request using the selectively activated components of the computing unit. As one example, the computing unit may comprise a laptop, and the external source may comprise a PDA, and the request may include a request from the PDA to retrieve data from or store data on the laptop.

    摘要翻译： 一种用于在计算单元中节省能量并在计算单元和外部源之间传送数据的方法。 计算单元处于省电模式。 该方法包括在计算单元处接收来自外部源的请求，确定需要计算单元的哪些组件来响应该请求，从功率节省模式选择性地激活响应请求所需的计算单元的组件 并且使用计算单元的选择性激活的组件来响应该请求。 作为一个示例，计算单元可以包括膝上型计算机，并且外部源可以包括PDA，并且该请求可以包括来自PDA以从笔记本电脑上检索数据或从笔记本电脑存储数据的请求。