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1.发明申请STRUCTURE AND METHOD OF MAKING STRAINED CHANNEL CMOS TRANSISTORS HAVING LATTICE-MISMATCHED EPITAXIAL EXTENSION AND SOURCE AND DRAIN REGIONS 有权具有狭缝分离的外延延伸和源和漏区的应变通道CMOS晶体管的结构和方法公开(公告)号：US20050051851A1
公开(公告)日：2005-03-10
申请号：US10605134
申请日：2003-09-10
IPC分类号： H01L21/265 , H01L21/336 , H01L21/8238 , H01L29/78 , H01L27/10 , H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L29/6653 , H01L21/26586 , H01L21/823807 , H01L21/823814 , H01L21/823835 , H01L21/823864 , H01L29/665 , H01L29/6656 , H01L29/7833 , H01L29/7848
摘要： A structure and method are provided in which an n-type field effect transistor (NFET) and a p-type field effect transistor (PFET) each have a channel region disposed in a single-crystal layer of a first semiconductor and a stress is applied at a first magnitude to a channel region of the PFET but not at that magnitude to the channel region of the NFET. The stress is applied by a layer of a second semiconductor which is lattice-mismatched to the first semiconductor. The layer of second semiconductor is formed over the source and drain regions and extensions of the PFET at a first distance from the channel region of the PFET and is formed over the source and drain regions of the NFET at a second, greater distance from the channel region of the NFET, or not formed at all in the NFET.
摘要翻译： 提供了一种结构和方法，其中n型场效应晶体管（NFET）和p型场效应晶体管（PFET）各自具有设置在第一半导体的单晶层中的沟道区域并施加应力 在第一幅度上与PFET的沟道区不同，但与NFET的沟道区不同。 应力由第一半导体晶格失配的第二半导体层施加。 第二半导体层形成在PFET的源极和漏极区域以及与PFET的沟道区第一距离处的延伸部分之间，并且形成在NFET的源极和漏极区域之上，距离沟道的第二更远的距离 NFET的区域，或者根本不形成在NFET中。
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2.发明申请Method of making strained channel CMOS transistors having lattice-mismatched epitaxial 有权制造具有晶格失配外延的应变通道CMOS晶体管的方法公开(公告)号：US20050148133A1
公开(公告)日：2005-07-07
申请号：US11052675
申请日：2005-02-07
申请人： Huaje Chen , Dureseti Chidambarrao , Omer Dokumaci , Haining Yang
发明人： Huaje Chen , Dureseti Chidambarrao , Omer Dokumaci , Haining Yang
IPC分类号： H01L21/265 , H01L21/336 , H01L21/8238 , H01L29/78 , H01L29/00
CPC分类号： H01L29/6653 , H01L21/26586 , H01L21/823807 , H01L21/823814 , H01L21/823835 , H01L21/823864 , H01L29/665 , H01L29/6656 , H01L29/7833 , H01L29/7848
摘要： A method is provided in which an n-type field effect transistor (NFET) and a p-type field effect transistor (PFET) each have a channel region disposed in a first single-crystal semiconductor region having a first composition. A stress is applied at a first magnitude to a channel region of the PFET but not at that magnitude to the channel region of the NFET. The stress is applied by a single-crystal semiconductor layer having a second composition such that the single-crystal semiconductor layer is lattice-mismatched to the first region. The semiconductor layer is formed over the source and drain regions and optionally over the extension regions of the PFET at a first distance from the channel region of the PFET and is formed over the source and drain regions of the NFET at a second, greater distance from the channel region of the NFET, or the semiconductor layer having the second composition is not formed at all in the NFET.
摘要翻译： 提供一种方法，其中n型场效应晶体管（NFET）和p型场效应晶体管（PFET）各自具有设置在具有第一组成的第一单晶半导体区域中的沟道区。 应力以第一幅度施加到PFET的沟道区，但不以该尺寸施加到NFET的沟道区。 应力由具有第二组成的单晶半导体层施加使得单晶半导体层与第一区域晶格失配。 半导体层形成在源极和漏极区域上，并且任选地在距离PFET的沟道区第一距离处的PFET的延伸区域上方形成，并且形成在NFET的源极和漏极区域之上，距离 NFET的沟道区域或具有第二组成的半导体层完全不形成在NFET中。
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3.发明申请Method of making strained semiconductor transistors having lattice-mismatched semiconductor regions underlying source and drain regions 有权制造应变半导体晶体管的方法，其具有位于源极和漏极区域之下的晶格失配的半导体区域公开(公告)号：US20070249114A1
公开(公告)日：2007-10-25
申请号：US11820303
申请日：2007-06-18
IPC分类号： H01L21/8238
CPC分类号： H01L21/84 , H01L21/02532 , H01L21/02636 , H01L21/823807 , H01L21/823814 , H01L27/0922 , H01L27/1203 , H01L29/165 , H01L29/6656 , H01L29/66628 , H01L29/66636 , H01L29/7848
摘要： A process is provided for making a PFET and an NFET. Areas in a first semiconductor region adjacent to a gate stack are recessed. A lattice-mismatched semiconductor layer is grown in the recesses to apply a strain to the channel region of the PFET adjacent thereto. A layer of the first semiconductor material can be grown over the lattice-mismatched semiconductor layer and a salicide formed from the layer of silicon to provide low-resistance source and drain regions.
摘要翻译： 提供了用于制造PFET和NFET的工艺。 与栅堆叠相邻的第一半导体区域中的区域是凹进的。 在凹槽中生长晶格不匹配的半导体层以向与其相邻的PFET的沟道区施加应变。 可以在晶格失配的半导体层上生长第一半导体材料层，以及由硅层形成的硅化物以提供低电阻源极和漏极区域。
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4.发明申请STRUCTURE AND METHOD OF MAKING STRAINED SEMICONDUCTOR CMOS TRANSISTORS HAVING LATTICE-MISMATCHED SOURCE AND DRAIN REGIONS 有权制造具有不匹配的源和漏区的应变半导体CMOS晶体管的结构和方法公开(公告)号：US20050029601A1
公开(公告)日：2005-02-10
申请号：US10604607
申请日：2003-08-04
IPC分类号： H01L21/20 , H01L21/336 , H01L21/8238 , H01L21/84 , H01L27/092 , H01L27/12 , H01L27/108 , C30B1/00 , H01L29/94 , H01L31/036
CPC分类号： H01L21/84 , H01L21/02532 , H01L21/02636 , H01L21/823807 , H01L21/823814 , H01L27/0922 , H01L27/1203 , H01L29/165 , H01L29/6656 , H01L29/66628 , H01L29/66636 , H01L29/7848
摘要： A p-type field effect transistor (PFET) and an n-type field effect transistor (NFET) of an integrated circuit are provided. A first strain is applied to the channel region of the PFET but not the NFET via a lattice-mismatched semiconductor layer such as silicon germanium disposed in source and drain regions of only the PFET and not of the NFET. A process of making the PFET and NFET is provided. Trenches are etched in the areas to become the source and drain regions of the PFET and a lattice-mismatched silicon germanium layer is grown epitaxially therein to apply a strain to the channel region of the PFET adjacent thereto. A layer of silicon can be grown over the silicon germanium layer and a salicide formed from the layer of silicon to provide low-resistance source and drain regions.
摘要翻译： 提供集成电路的p型场效应晶体管（PFET）和n型场效应晶体管（NFET）。 第一应变施加到PFET的沟道区，而不是NFET通过位于仅仅PFET而不是NFET的源极和漏极区域中的晶格不匹配的半导体层，例如硅锗。 提供制造PFET和NFET的工艺。 在区域中蚀刻沟槽以成为PFET的源极和漏极区域，并且将晶格失配的硅锗层外延生长以向与其相邻的PFET的沟道区域施加应变。 可以在硅锗层上生长一层硅层，并从硅层形成硅化物以提供低电阻源极和漏极区域。
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5.发明申请Method of making strained semiconductor transistors having lattice-mismatched semiconductor regions underlying source and drain regions 失效制造应变半导体晶体管的方法，其具有位于源极和漏极区域之下的晶格失配的半导体区域公开(公告)号：US20050158931A1
公开(公告)日：2005-07-21
申请号：US11081271
申请日：2005-03-16
IPC分类号： H01L21/20 , H01L21/336 , H01L21/8238 , H01L21/84 , H01L27/092 , H01L27/12 , H01L21/337
CPC分类号： H01L21/84 , H01L21/02532 , H01L21/02636 , H01L21/823807 , H01L21/823814 , H01L27/0922 , H01L27/1203 , H01L29/165 , H01L29/6656 , H01L29/66628 , H01L29/66636 , H01L29/7848
摘要： A p-type field effect transistor (PFET) and an n-type field effect transistor (NFET) of an integrated circuit are provided. A first strain is applied to the channel region of the PFET but not the NFET via a lattice-mismatched semiconductor layer such as silicon germanium disposed in source and drain regions of only the PFET and not of the NFET. A process of making the PFET and NFET is provided. Trenches are etched in the areas to become the source and drain regions of the PFET and a lattice-mismatched silicon germanium layer is grown epitaxially therein to apply a strain to the channel region of the PFET adjacent thereto. A layer of silicon can be grown over the silicon germanium layer and a salicide formed from the layer of silicon to provide low-resistance source and drain regions.
摘要翻译： 提供集成电路的p型场效应晶体管（PFET）和n型场效应晶体管（NFET）。 第一应变施加到PFET的沟道区，而不是NFET通过位于仅仅PFET而不是NFET的源极和漏极区域中的晶格不匹配的半导体层，例如硅锗。 提供制造PFET和NFET的工艺。 在区域中蚀刻沟槽以成为PFET的源极和漏极区域，并且将晶格失配的硅锗层外延生长以向与其相邻的PFET的沟道区域施加应变。 可以在硅锗层上生长一层硅层，并从硅层形成硅化物以提供低电阻源极和漏极区域。
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公开(公告)号：US07737014B2
公开(公告)日：2010-06-15
申请号：US10596249
申请日：2003-12-08
申请人： Frederick William Buehrer , Dureseti Chidambarrao , Bruce B. Doris , Hsiang-Jen Huang , Haining Yang
发明人： Frederick William Buehrer , Dureseti Chidambarrao , Bruce B. Doris , Hsiang-Jen Huang , Haining Yang
CPC分类号： H01L29/7842 , H01L21/22 , H01L21/26513 , H01L21/26586 , H01L21/324 , H01L21/823807 , H01L21/823814 , H01L29/1083 , H01L29/6653 , H01L29/6656 , H01L29/6659 , H01L29/7843
摘要： A stressed film applied across a boundary defined by a structure or a body (e.g. substrate or layer) of semiconductor material provides a change from tensile to compressive stress in the semiconductor material proximate to the boundary and is used to modify boron diffusion rate during annealing and thus modify final boron concentrations. In the case of a field effect transistor, the gate structure may be formed with or without sidewalls to regulate the location of the boundary relative to source/drain, extension and/or halo implants. Different boron diffusion rates can be produced in the lateral and vertical directions and diffusion rates comparable to arsenic can be achieved. Reduction of junction capacitance of both nFETs and pFETs can be achieved simultaneously with the same process steps.
摘要翻译： 应用于由半导体材料的结构或主体（例如衬底或层）限定的边界处的应力膜提供了靠近边界的半导体材料中的拉应力和压缩应力的变化，并用于在退火过程中修饰硼扩散速率， 从而改变最终的硼浓度。 在场效应晶体管的情况下，栅极结构可以形成有或不具有侧壁以调节边界相对于源极/漏极，延伸和/或晕轮植入物的位置。 可以在横向和垂直方向上产生不同的硼扩散速率，并且可以实现与砷相当的扩散速率。 可以通过相同的工艺步骤同时实现nFET和pFET的结电容的减小。
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公开(公告)号：US07732270B2
公开(公告)日：2010-06-08
申请号：US11972964
申请日：2008-01-11
申请人： Dureseti Chidambarrao , Ying Li , Rajeev Malik , Shreesh Narasimha , Haining Yang , Huilong Zhu
发明人： Dureseti Chidambarrao , Ying Li , Rajeev Malik , Shreesh Narasimha , Haining Yang , Huilong Zhu
IPC分类号： H01L21/8238
CPC分类号： H01L29/7843 , H01L21/823807 , H01L29/66772 , Y10S438/938
摘要： The present invention provides a semiconductor device having dual nitride liners, which provide an increased transverse stress state for at least one FET and methods for the manufacture of such a device. A first aspect of the invention provides a method for use in the manufacture of a semiconductor device comprising the steps of applying a first silicon nitride liner to the device and applying a second silicon nitride liner adjacent the first silicon nitride liner, wherein at least one of the first and second silicon nitride liners induces a transverse stress in a silicon channel beneath at least one of the first and second silicon nitride liner.
摘要翻译： 本发明提供一种具有双重氮化物衬垫的半导体器件，其为至少一个FET提供增加的横向应力状态以及用于制造这种器件的方法。 本发明的第一方面提供了一种用于制造半导体器件的方法，包括以下步骤：将第一氮化硅衬垫施加到器件上并施加与第一氮化硅衬垫相邻的第二氮化硅衬垫，其中至少一个 第一和第二氮化硅衬垫在第一和第二氮化硅衬里中的至少一个之下的硅沟道中引起横向应力。
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公开(公告)号：US20070093030A1
公开(公告)日：2007-04-26
申请号：US10596249
申请日：2003-12-08
IPC分类号： H01L21/336 , H01L21/322 , H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L29/7842 , H01L21/22 , H01L21/26513 , H01L21/26586 , H01L21/324 , H01L21/823807 , H01L21/823814 , H01L29/1083 , H01L29/6653 , H01L29/6656 , H01L29/6659 , H01L29/7843
摘要： A stressed film applied across a boundary defined by a structure or a body (e.g. substrate or layer) of semiconductor material provides a change from tensile to compressive stress in the semiconductor material proximate to the boundary and is used to modify boron diffusion rate during annealing and thus modify final boron concentrations. In the case of a field effect transistor, the gate structure may be formed with or without sidewalls to regulate the location of the boundary relative to source/drain, extension and/or halo implants. Different boron diffusion rates can be produced in the lateral and vertical directions and diffusion rates comparable to arsenic can be achieved. Reduction of junction capacitance of both nFETs and pFETs can be achieved simultaneously with the same process steps.
摘要翻译： 应用于由半导体材料的结构或主体（例如衬底或层）限定的边界处的应力膜提供了靠近边界的半导体材料中的拉应力和压缩应力的变化，并用于在退火过程中修饰硼扩散速率， 从而改变最终的硼浓度。 在场效应晶体管的情况下，栅极结构可以形成有或不具有侧壁以调节边界相对于源极/漏极，延伸和/或晕轮植入物的位置。 可以在横向和垂直方向上产生不同的硼扩散速率，并且可以实现与砷相当的扩散速率。 可以通过相同的工艺步骤同时实现nFET和pFET的结电容的减小。
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公开(公告)号：US20060128091A1
公开(公告)日：2006-06-15
申请号：US10905025
申请日：2004-12-10
申请人： Dureseti Chidambarrao , Ying Li , Rajeev Malik , Shreesh Narasimha , Haining Yang , Huilong Zhu
发明人： Dureseti Chidambarrao , Ying Li , Rajeev Malik , Shreesh Narasimha , Haining Yang , Huilong Zhu
IPC分类号： H01L21/8238
CPC分类号： H01L29/7843 , H01L21/823807 , H01L29/66772 , Y10S438/938
摘要： The present invention provides a semiconductor device having dual nitride liners, which provide an increased transverse stress state for at least one FET and methods for the manufacture of such a device. A first aspect of the invention provides a method for use in the manufacture of a semiconductor device comprising the steps of applying a first silicon nitride liner to the device and applying a second silicon nitride liner adjacent the first silicon nitride liner, wherein at least one of the first and second silicon nitride liners induces a transverse stress in a silicon channel beneath at least one of the first and second silicon nitride liner.
摘要翻译： 本发明提供一种具有双重氮化物衬垫的半导体器件，其为至少一个FET提供增加的横向应力状态以及用于制造这种器件的方法。 本发明的第一方面提供了一种用于制造半导体器件的方法，包括以下步骤：将第一氮化硅衬垫施加到器件上并施加与第一氮化硅衬垫相邻的第二氮化硅衬垫，其中至少一个 第一和第二氮化硅衬垫在第一和第二氮化硅衬里中的至少一个之下的硅沟道中引起横向应力。
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公开(公告)号：US20080108228A1
公开(公告)日：2008-05-08
申请号：US11972964
申请日：2008-01-11
申请人： Dureseti Chidambarrao , Ying Li , Rajeev Malik , Shreesh Narasimha , Haining Yang , Huilong Zhu
发明人： Dureseti Chidambarrao , Ying Li , Rajeev Malik , Shreesh Narasimha , Haining Yang , Huilong Zhu
IPC分类号： H01L21/31
CPC分类号： H01L29/7843 , H01L21/823807 , H01L29/66772 , Y10S438/938
摘要： The present invention provides a semiconductor device having dual nitride liners, which provide an increased transverse stress state for at least one FET and methods for the manufacture of such a device. A first aspect of the invention provides a method for use in the manufacture of a semiconductor device comprising the steps of applying a first silicon nitride liner to the device and applying a second silicon nitride liner adjacent the first silicon nitride liner, wherein at least one of the first and second silicon nitride liners induces a transverse stress in a silicon channel beneath at least one of the first and second silicon nitride liner.
摘要翻译： 本发明提供一种具有双重氮化物衬垫的半导体器件，其为至少一个FET提供增加的横向应力状态以及用于制造这种器件的方法。 本发明的第一方面提供了一种用于制造半导体器件的方法，包括以下步骤：将第一氮化硅衬垫施加到器件上并施加与第一氮化硅衬垫相邻的第二氮化硅衬垫，其中至少一个 第一和第二氮化硅衬垫在第一和第二氮化硅衬里中的至少一个之下的硅沟道中引起横向应力。
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