公开(公告)号：US20240338328A1

公开(公告)日：2024-10-10

申请号：US18744042

申请日：2024-06-14

Applicant: Huawei Technologies Co., Ltd.

Inventor： Wen Yin ,  Wei Li ,  Yigang Zhou ,  Manbo Wu ,  Xianzhou Lin ,  Chuanwei Wen ,  Ruonan Wang ,  Yining Li

IPC: G06F13/16 ,  G06F13/18 ,  G06F13/40 ,  G06F13/42

CPC classification number: G06F13/1668 ,  G06F13/18 ,  G06F13/409 ,  G06F13/4243

Abstract: A data processing system includes a computing subsystem and a memory subsystem. In the computing subsystem, a processor is connected to one end of a high-speed parallel bus via a first bus interface. The processor transmits data to the memory subsystem and receives data transmitted through the high-speed parallel bus. The memory subsystem receives and transmits data to the computing subsystem through the high-speed parallel bus.