公开(公告)号：US20240338328A1

公开(公告)日：2024-10-10

申请号：US18744042

申请日：2024-06-14

Applicant: Huawei Technologies Co., Ltd.

Inventor： Wen Yin ,  Wei Li ,  Yigang Zhou ,  Manbo Wu ,  Xianzhou Lin ,  Chuanwei Wen ,  Ruonan Wang ,  Yining Li

IPC: G06F13/16 ,  G06F13/18 ,  G06F13/40 ,  G06F13/42

CPC classification number: G06F13/1668 ,  G06F13/18 ,  G06F13/409 ,  G06F13/4243

Abstract: A data processing system includes a computing subsystem and a memory subsystem. In the computing subsystem, a processor is connected to one end of a high-speed parallel bus via a first bus interface. The processor transmits data to the memory subsystem and receives data transmitted through the high-speed parallel bus. The memory subsystem receives and transmits data to the computing subsystem through the high-speed parallel bus.

公开(公告)号：US20230185901A1

公开(公告)日：2023-06-15

申请号：US18067797

申请日：2022-12-19

Applicant: HUAWEI TECHNOLOGIES CO., LTD.

Inventor： Wen Yin ,  Hong Li ,  Yingxin Qiu ,  Xiaowei Lin

IPC: G06F21/53

CPC classification number: G06F21/53 ,  G06F2221/2105

Abstract: A data processing host includes a program running environment and a first isolation environment. The first isolation environment is isolated from the program running environment. The host operates in a non-secure mode in the program running environment, and operates in a secure mode in the first isolation environment. The program running environment includes a virtual instance operating in the non-secure mode, and the first isolation environment corresponds to the virtual instance in the program running environment. The first isolation environment includes an operating system in the secure mode and a resource allocated to the first isolation environment and comprising a first isolation space for running the operation system and a secure processing program, which corresponds to a program in the virtual instance and is for processing to-be-processed data.

公开(公告)号：US20230132748A1

公开(公告)日：2023-05-04

申请号：US18069800

申请日：2022-12-21

Applicant: HUAWEI TECHNOLOGIES CO., LTD.

Inventor： Wen Yin

IPC: H01L29/06

Abstract: A field effect transistor and a preparation method thereof, and a semiconductor structure are provided. An example field effect transistor includes: a substrate structure, a source, a drain, and a gate. The source and the drain are arranged on the substrate structure in a first direction, and a channel region is formed between the source and the drain. A channel layer is formed in the channel region, and N carbon nanotubes extending in the first direction are embedded in the channel layer, where N is an integer greater than or equal to 1. Two ends of each of the N carbon nanotubes are respectively connected to the source and the drain to form a conductive path. The gate is formed on the channel layer. In the channel region between the source and the drain, electron conduction is implemented by using the carbon nanotube disposed in the channel layer.

公开(公告)号：US12287665B2

公开(公告)日：2025-04-29

申请号：US17947699

申请日：2022-09-19

Applicant: HUAWEI TECHNOLOGIES CO., LTD.

Inventor： Wen Yin

IPC: G06F1/08 ,  G06F1/06 ,  G06F1/10 ,  G06F1/3237 ,  G06F1/324 ,  H01L23/00 ,  H01L23/498 ,  H03L7/08 ,  H01L25/065

Abstract: A clock circuit constructed in a processor integrated circuit includes a phase lock loop PLL, a clock tree, and a clock grid. The clock tree includes a plurality of clock buffers in a layered structure, The clock tree is configured to receive a first clock signal clk_1 that is output by the phase lock loop PLL, and to output a second clock signal clk_2. A plurality of child node circuits (400) are disposed on some nodes of the clock grid, and are configured to generate a third clock signal clk_3 based on the second clock signal clk_2. The clock grid (330) and the clock tree (320) are distributed on multiple dies in a three-dimensional structure of the processor integrated circuit.

公开(公告)号：US20220327070A1

公开(公告)日：2022-10-13

申请号：US17846522

申请日：2022-06-22

Applicant: Huawei Technologies Co., Ltd.

Inventor： Wen Yin

IPC: G06F13/16 ,  G06F13/38 ,  G06F13/42 ,  G06F12/0862

Abstract: A memory manager disposed between a memory and a processor. One end of the memory manager is coupled to the processor using a serial line, and the other end of the memory manager is coupled to the memory using a parallel line to provide the processor with a serial interface instead of a parallel interface.