摘要:
The present application discloses provides a method for planarizing an interlayer dielectric layer, comprising the steps of: providing a multilayer structure including at least one sacrificial layer and at least one insulating layer under the sacrificial layer on the semiconductor substrate and the first gate stack, performing a first RIE on the multilayer structure, in which a reaction chamber pressure is controlled in such a manner that an etching rate of the portion of the at least one sacrificial layer at a center of a wafer is higher than that at an edge of the wafer, so as to obtain a concave etching profile; performing a second RIE on the multilayer structure to completely remove the sacrificial layer and a part of the insulating layer, so as to obtain the insulating layer having a planar surface which serves as an interlayer dielectric layer. The planarization process can replace a CMP process for providing an interlayer dielectric layer having a planar surface, which achieves a relative larger available area of the wafer.
摘要:
A method for manufacturing a semiconductor device includes the steps of: forming a first gate stack on a semiconductor substrate, the first gate stack includes a first gate conductor and a first gate dielectric between the first gate conductor and the semiconductor substrate; forming source/drain regions on the semiconductor substrate; forming a multilayer structure including at least one sacrificial layer and at least one insulating layer under the sacrificial layer on the semiconductor substrate and the first gate stack; performing a first RIE on the multilayer structure; performing a second RIE on the multilayer structure; selectively etching the first gate stack with respect to the insulating layer, in which the first gate conductor is removed and an opening is formed in the insulating layer; and forming a second gate conductor in the opening.
摘要:
The present application discloses provides a method for planarizing an interlayer dielectric layer, comprising the steps of: providing a multilayer structure including at least one sacrificial layer and at least one insulating layer under the sacrificial layer on the semiconductor substrate and the first gate stack, performing a first RIE on the multilayer structure, in which a reaction chamber pressure is controlled in such a manner that an etching rate of the portion of the at least one sacrificial layer at a center of a wafer is higher than that at an edge of the wafer, so as to obtain a concave etching profile; performing a second RIE on the multilayer structure to completely remove the sacrificial layer and a part of the insulating layer, so as to obtain the insulating layer having a planar surface which serves as an interlayer dielectric layer. The planarization process can replace a CMP process for providing an interlayer dielectric layer having a planar surface, which achieves a relative larger available area of the wafer.
摘要:
A method for manufacturing a semiconductor device includes the steps of: forming a first gate stack on a semiconductor substrate, the first gate stack includes a first gate conductor and a first gate dielectric between the first gate conductor and the semiconductor substrate; forming source/drain regions on the semiconductor substrate; forming a multilayer structure including at least one sacrificial layer and at least one insulating layer under the sacrificial layer on the semiconductor substrate and the first gate stack; performing a first RIE on the multilayer structure; performing a second RIE on the multilayer structure; selectively etching the first gate stack with respect to the insulating layer, in which the first gate conductor is removed and an opening is formed in the insulating layer; and forming a second gate conductor in the opening.
摘要:
A semiconductor device manufacturing method, comprising: providing a semiconductor substrate, on which a gate conductor layer as well as a source region and a drain region positioned on both sides of the gate conductor layer are provided, forming an etch stop layer on the semiconductor substrate, forming an LTO layer on the etch stop layer, chemical mechanical polishing the LTO layer, forming an SOG layer on the polished LTO layer, the etch stop layer, LTO layer and SOG layer forming a front metal insulating layer, back etching the SOG layer and etch stop layer of the front metal insulating layer to expose the gate conductor layer, and removing the gate conductor layer.
摘要:
A semiconductor device manufacturing method, comprising: providing a semiconductor substrate, on which a gate conductor layer as well as a source region and a drain region positioned on both sides of the gate conductor layer are provided, forming an etch stop layer on the semiconductor substrate, forming an LTO layer on the etch stop layer, chemical mechanical polishing the LTO layer, forming an SOG layer on the polished LTO layer, the etch stop layer, LTO layer and SOG layer forming a front metal insulating layer, back etching the SOG layer and etch stop layer of the front metal insulating layer to expose the gate conductor layer, and removing the gate conductor layer.
摘要:
The invention discloses an etch-back method for planarization at the position-near-interface of an interlayer dielectric (ILD), comprising: depositing or growing a thick layer of SiO2 by the chemical vapor deposition or oxidation method on a surface of a wafer; spin-coating a layer of SOG and then performing a heat treatment to obtain a relatively uniform stack structure; perform an etch-back on the SOG using a plasma etching, and stopping when approaching the position-near-interface of SiO2; performing a plasma etch-back on the remaining SOG/SiO2 structure at the position-near-interface until achieving a desired thickness. Since a two-step etching at the position-near-interface is employed, an extremely good smooth surface of the ILD is obtained. That is, a planar and tidy surface of the ILD is obtained not only in the center region, but also even at the edge of the wafer.
摘要:
A method of manufacturing a semiconductor device is disclosed. The method may comprise: forming a gate stack on a substrate; depositing a first dielectric layer and a second dielectric layer sequentially on the substrate and the gate stack; and etching the second dielectric layer and the first dielectric layer sequentially with an etching gas containing helium to form a second spacer and a first spacer, respectively. According to the method disclosed herein, a dual-layer complex spacer configuration is achieved, and two etching operations where the etching gas comprises the helium gas are performed. As a result, it is possible to reduce damages to the substrate and also to reduce the process complexity. Further, it is possible to optimize a threshold voltage, effectively reduce an EOT, and enhance a gate control capability and a driving current.
摘要:
The present invention relates to a thin film filling method, including: feeding reactive gases including a silicon-containing gas, an oxygen-containing gas, an inert gas and a fluent gas into a reaction chamber; forming a first deposited thin film in the trench or gap through HDP CVD; feeding an etching gas and the fluent gas without feeding said silicon-containing gas and oxygen-containing gas, to sputter the surface of the first deposited thin film; feeding said silicon-containing gas and oxygen-containing gas without feeding said etching gas, so that a second deposited thin film is formed on the surface of the sputtered first deposited thin film; feeding said etching gas and fluent gas without feeding said silicon-containing gas and oxygen-containing gas, to sputtering the surface of said second deposited thin film; repeating the last two steps; feeding the silicon-containing gas and oxygen-containing gas without feeding the etching gas to form a plasmas of low pressure and high density, so that a third deposited thin film, which completely fills said trench or gap, is formed on the surface of the sputtered second deposited thin film.
摘要:
A method of manufacturing a semiconductor device is disclosed. The method may comprise: etching a plurality of first openings in an interlayer dielectric layer on a substrate; forming an opening modifying layer in the plurality of first openings; and etching the opening modifying layer until the substrate is exposed, resulting in a plurality of second openings, wherein the second openings have a depth-to-width ratio greater than that of the first openings. In this way, a deep hole with a relatively large dimension can be formed in silicon oxide by conventional photolithography processes. After that, a film of silicon nitride can be deposited into the hole to achieve a desired CD, and then etched with the fluorocarbon gas(es) to implement an arrangement with a relatively great depth-to-width ratio.