公开(公告)号：US20120164808A1

公开(公告)日：2012-06-28

申请号：US13129419

申请日：2011-02-17

申请人： Huaxiang Yin ,  Qiuxia Xu ,  Gaobo Xu ,  Lingkuan Meng ,  Tao Yang ,  Dapeng Chen

发明人： Huaxiang Yin ,  Qiuxia Xu ,  Gaobo Xu ,  Lingkuan Meng ,  Tao Yang ,  Dapeng Chen

IPC分类号： H01L21/336

CPC分类号： H01L21/823842 ,  H01L21/31055 ,  H01L21/31116 ,  H01L21/76819 ,  H01L29/66545 ,  H01L29/78

摘要： A method for manufacturing a semiconductor device includes the steps of: forming a first gate stack on a semiconductor substrate, the first gate stack includes a first gate conductor and a first gate dielectric between the first gate conductor and the semiconductor substrate; forming source/drain regions on the semiconductor substrate; forming a multilayer structure including at least one sacrificial layer and at least one insulating layer under the sacrificial layer on the semiconductor substrate and the first gate stack; performing a first RIE on the multilayer structure; performing a second RIE on the multilayer structure; selectively etching the first gate stack with respect to the insulating layer, in which the first gate conductor is removed and an opening is formed in the insulating layer; and forming a second gate conductor in the opening.

摘要翻译： 一种制造半导体器件的方法包括以下步骤：在半导体衬底上形成第一栅极叠层，第一栅叠层在第一栅极导体和半导体衬底之间包括第一栅极导体和第一栅极电介质; 在半导体衬底上形成源/漏区; 在所述半导体衬底和所述第一栅极叠层上形成包括至少一个牺牲层和所述牺牲层下方的至少一个绝缘层的多层结构; 在所述多层结构上执行第一RIE; 在所述多层结构上执行第二RIE; 相对于绝缘层选择性地蚀刻第一栅极叠层，其中去除第一栅极导体并在绝缘层中形成开口; 以及在所述开口中形成第二栅极导体。

公开(公告)号：US08324061B2

公开(公告)日：2012-12-04

申请号：US13129419

申请日：2011-02-17

申请人： Huaxiang Yin ,  Qiuxia Xu ,  Gaobo Xu ,  Lingkuan Meng ,  Tao Yang ,  Dapeng Chen

发明人： Huaxiang Yin ,  Qiuxia Xu ,  Gaobo Xu ,  Lingkuan Meng ,  Tao Yang ,  Dapeng Chen

IPC分类号： H01L21/336

CPC分类号： H01L21/823842 ,  H01L21/31055 ,  H01L21/31116 ,  H01L21/76819 ,  H01L29/66545 ,  H01L29/78

摘要： A method for manufacturing a semiconductor device includes the steps of: forming a first gate stack on a semiconductor substrate, the first gate stack includes a first gate conductor and a first gate dielectric between the first gate conductor and the semiconductor substrate; forming source/drain regions on the semiconductor substrate; forming a multilayer structure including at least one sacrificial layer and at least one insulating layer under the sacrificial layer on the semiconductor substrate and the first gate stack; performing a first RIE on the multilayer structure; performing a second RIE on the multilayer structure; selectively etching the first gate stack with respect to the insulating layer, in which the first gate conductor is removed and an opening is formed in the insulating layer; and forming a second gate conductor in the opening.

摘要翻译： 一种制造半导体器件的方法包括以下步骤：在半导体衬底上形成第一栅极叠层，第一栅叠层在第一栅极导体和半导体衬底之间包括第一栅极导体和第一栅极电介质; 在半导体衬底上形成源/漏区; 在所述半导体衬底和所述第一栅极叠层上形成包括至少一个牺牲层和所述牺牲层下方的至少一个绝缘层的多层结构; 在所述多层结构上执行第一RIE; 在所述多层结构上执行第二RIE; 相对于绝缘层选择性地蚀刻第一栅极叠层，其中去除第一栅极导体并在绝缘层中形成开口; 以及在所述开口中形成第二栅极导体。

公开(公告)号：US08703617B2

公开(公告)日：2014-04-22

申请号：US13147044

申请日：2011-02-17

申请人： Huaxiang Yin ,  Qiuxia Xu ,  Lingkuan Meng ,  Tao Yang ,  Dapeng Chen

发明人： Huaxiang Yin ,  Qiuxia Xu ,  Lingkuan Meng ,  Tao Yang ,  Dapeng Chen

IPC分类号： H01L21/302 ,  H01L21/461 ,  B44C1/22 ,  C03C15/00 ,  C03C25/68 ,  C23F1/00

CPC分类号： H01L21/76819 ,  H01L21/31055 ,  H01L21/31116

摘要： The present application discloses provides a method for planarizing an interlayer dielectric layer, comprising the steps of: providing a multilayer structure including at least one sacrificial layer and at least one insulating layer under the sacrificial layer on the semiconductor substrate and the first gate stack, performing a first RIE on the multilayer structure, in which a reaction chamber pressure is controlled in such a manner that an etching rate of the portion of the at least one sacrificial layer at a center of a wafer is higher than that at an edge of the wafer, so as to obtain a concave etching profile; performing a second RIE on the multilayer structure to completely remove the sacrificial layer and a part of the insulating layer, so as to obtain the insulating layer having a planar surface which serves as an interlayer dielectric layer. The planarization process can replace a CMP process for providing an interlayer dielectric layer having a planar surface, which achieves a relative larger available area of the wafer.

摘要翻译： 本申请公开提供了一种用于平坦化层间电介质层的方法，包括以下步骤：提供包括至少一个牺牲层和在半导体衬底和第一栅极叠层下的牺牲层下方的至少一个绝缘层的多层结构，执行 多层结构中的第一RIE，其中反应室压力被控制为使得晶片中心处的至少一个牺牲层的部分的蚀刻速率高于晶片的边缘处的蚀刻速率 ，以获得凹蚀刻轮廓; 在所述多层结构上执行第二RIE以完全去除所述牺牲层和所述绝缘层的一部分，从而获得具有用作层间介质层的平坦表面的所述绝缘层。 平坦化处理可以代替用于提供具有平坦表面的层间介电层的CMP工艺，其实现了晶片的相对较大的可用面积。

公开(公告)号：US20120164838A1

公开(公告)日：2012-06-28

申请号：US13147044

申请日：2011-02-17

申请人： Huaxiang Yin ,  Qiuxia Xu ,  Lingkuan Meng ,  Tao Yang ,  Dapeng Chen

发明人： Huaxiang Yin ,  Qiuxia Xu ,  Lingkuan Meng ,  Tao Yang ,  Dapeng Chen

IPC分类号： H01L21/263

CPC分类号： H01L21/76819 ,  H01L21/31055 ,  H01L21/31116

摘要： The present application discloses provides a method for planarizing an interlayer dielectric layer, comprising the steps of: providing a multilayer structure including at least one sacrificial layer and at least one insulating layer under the sacrificial layer on the semiconductor substrate and the first gate stack, performing a first RIE on the multilayer structure, in which a reaction chamber pressure is controlled in such a manner that an etching rate of the portion of the at least one sacrificial layer at a center of a wafer is higher than that at an edge of the wafer, so as to obtain a concave etching profile; performing a second RIE on the multilayer structure to completely remove the sacrificial layer and a part of the insulating layer, so as to obtain the insulating layer having a planar surface which serves as an interlayer dielectric layer. The planarization process can replace a CMP process for providing an interlayer dielectric layer having a planar surface, which achieves a relative larger available area of the wafer.

摘要翻译： 本申请公开提供了一种用于平坦化层间电介质层的方法，包括以下步骤：提供包括至少一个牺牲层和在半导体衬底和第一栅极叠层下的牺牲层下方的至少一个绝缘层的多层结构，执行 多层结构中的第一RIE，其中反应室压力被控制为使得晶片中心处的至少一个牺牲层的部分的蚀刻速率高于晶片的边缘处的蚀刻速率 ，以获得凹蚀刻轮廓; 在所述多层结构上执行第二RIE以完全去除所述牺牲层和所述绝缘层的一部分，从而获得具有用作层间介质层的平坦表面的所述绝缘层。 平坦化处理可以代替用于提供具有平坦表面的层间介电层的CMP工艺，其实现了晶片的相对较大的可用面积。

公开(公告)号：US08664119B2

公开(公告)日：2014-03-04

申请号：US13497526

申请日：2011-11-28

申请人： Huaxiang Yin ,  Qiuxia Xu ,  Lingkuan Meng ,  Dapeng Chen

发明人： Huaxiang Yin ,  Qiuxia Xu ,  Lingkuan Meng ,  Dapeng Chen

IPC分类号： H01L21/311 ,  H01L21/461

CPC分类号： H01L21/31053 ,  H01L21/28079 ,  H01L21/28088 ,  H01L21/31055 ,  H01L21/31116 ,  H01L21/823807 ,  H01L29/66545

摘要： A semiconductor device manufacturing method, comprising: providing a semiconductor substrate, on which a gate conductor layer as well as a source region and a drain region positioned on both sides of the gate conductor layer are provided, forming an etch stop layer on the semiconductor substrate, forming an LTO layer on the etch stop layer, chemical mechanical polishing the LTO layer, forming an SOG layer on the polished LTO layer, the etch stop layer, LTO layer and SOG layer forming a front metal insulating layer, back etching the SOG layer and etch stop layer of the front metal insulating layer to expose the gate conductor layer, and removing the gate conductor layer.

摘要翻译： 一种半导体器件制造方法，包括：提供半导体衬底，在所述半导体衬底上设置栅极导体层以及位于所述栅极导体层两侧的源极区域和漏极区域，在所述半导体衬底上形成蚀刻停止层 在蚀刻停止层上形成LTO层，化学机械抛光LTO层，在抛光的LTO层上形成SOG层，形成前金属绝缘层的蚀刻停止层，LTO层和SOG层，背面蚀刻SOG层 和前金属绝缘层的蚀刻停止层，以露出栅极导体层，以及去除栅极导体层。

公开(公告)号：US20130137264A1

公开(公告)日：2013-05-30

申请号：US13497526

申请日：2011-11-28

申请人： Huaxiang Yin ,  Qiuxia Xu ,  Lingkuan Meng ,  Dapeng Chen

发明人： Huaxiang Yin ,  Qiuxia Xu ,  Lingkuan Meng ,  Dapeng Chen

IPC分类号： H01L21/306

CPC分类号： H01L21/31053 ,  H01L21/28079 ,  H01L21/28088 ,  H01L21/31055 ,  H01L21/31116 ,  H01L21/823807 ,  H01L29/66545

摘要： A semiconductor device manufacturing method, comprising: providing a semiconductor substrate, on which a gate conductor layer as well as a source region and a drain region positioned on both sides of the gate conductor layer are provided, forming an etch stop layer on the semiconductor substrate, forming an LTO layer on the etch stop layer, chemical mechanical polishing the LTO layer, forming an SOG layer on the polished LTO layer, the etch stop layer, LTO layer and SOG layer forming a front metal insulating layer, back etching the SOG layer and etch stop layer of the front metal insulating layer to expose the gate conductor layer, and removing the gate conductor layer.

摘要翻译： 一种半导体器件制造方法，包括：提供半导体衬底，在所述半导体衬底上设置栅极导体层以及位于所述栅极导体层两侧的源极区域和漏极区域，在所述半导体衬底上形成蚀刻停止层 在蚀刻停止层上形成LTO层，化学机械抛光LTO层，在抛光的LTO层上形成SOG层，形成前金属绝缘层的蚀刻停止层，LTO层和SOG层，背面蚀刻SOG层 和前金属绝缘层的蚀刻停止层，以露出栅极导体层，以及去除栅极导体层。

公开(公告)号：US20150170974A1

公开(公告)日：2015-06-18

申请号：US14355919

申请日：2012-12-07

申请人： Qiuxia Xu ,  Huilong Zhu ,  Gaobo Xu ,  Huajie Zhou ,  Dapeng Chen

发明人： Qiuxia Xu ,  Huilong Zhu ,  Gaobo Xu ,  Huajie Zhou ,  Dapeng Chen

IPC分类号： H01L21/8238 ,  H01L21/28 ,  H01L21/3105 ,  H01L21/321 ,  H01L21/324 ,  H01L29/167 ,  H01L21/266 ,  H01L29/66 ,  H01L29/51 ,  H01L29/423 ,  H01L29/49 ,  H01L21/3213 ,  H01L21/02

CPC分类号： H01L21/823857 ,  H01L21/0228 ,  H01L21/0254 ,  H01L21/266 ,  H01L21/28141 ,  H01L21/28176 ,  H01L21/31051 ,  H01L21/3212 ,  H01L21/3213 ,  H01L21/324 ,  H01L21/823842 ,  H01L29/167 ,  H01L29/42364 ,  H01L29/42372 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/78

摘要： A method for manufacturing a semiconductor device, comprising: defining an active region on the semiconductor substrate; forming an interfacial oxide layer on a surface of the semiconductor substrate; forming a high-K gate dielectric on the interfacial oxide layer; forming a first metal gate layer on the high-K gate dielectric; forming a dummy gate layer on the first metal gate layer; patterning the dummy gate layer, the first metal gate layer, the high-K gate dielectric and the interfacial oxide layer to form a gate stack structure; forming a gate spacer surrounding the gate stack structure; forming S/D regions for NMOS and PMOS respectively; depositing interlayer dielectric and planarization by CMP to expose the surface of dummy gate layer; removing the dummy gate layer so as to form a gate opening; implanting dopant ions into the first metal gate layer; forming a second metal gate layer on the first metal gate layer so as to fill the gate opening; and performing annealing, so that the dopant ions diffuse and accumulate at an upper interface between the high-K gate dielectric and the first metal gate layer and at a lower interface between the high-K gate dielectric and the interfacial oxide layer, and electric dipoles are generated by interfacial reaction at the lower interface between the high-K gate dielectric and the interfacial oxide layer.

摘要翻译： 一种制造半导体器件的方法，包括：在所述半导体衬底上限定有源区; 在所述半导体衬底的表面上形成界面氧化物层; 在界面氧化物层上形成高K栅电介质; 在高K栅极电介质上形成第一金属栅极层; 在所述第一金属栅极层上形成伪栅极层; 图案化虚拟栅极层，第一金属栅极层，高K栅极电介质和界面氧化物层以形成栅极堆叠结构; 形成围绕所述栅堆叠结构的栅极间隔; 分别形成NMOS和PMOS的S / D区域; 通过CMP沉积层间电介质和平面化以暴露虚拟栅极层的表面; 去除虚拟栅极层以形成栅极开口; 将掺杂剂离子注入到第一金属栅极层中; 在所述第一金属栅极层上形成第二金属栅极层以填充所述栅极开口; 并执行退火，使得掺杂剂离子在高K栅极电介质和第一金属栅极层之间以及高K栅极电介质和界面氧化物层之间的下界面处的上界面处扩散并积聚，并且电偶极子 通过界面反应在高K栅极电介质和界面氧化物层之间的下界面产生。

公开(公告)号：US20140231923A1

公开(公告)日：2014-08-21

申请号：US14346537

申请日：2012-05-16

申请人： Huaxiang Yin ,  Qiuxia Xu ,  Dapeng Chen

发明人： Huaxiang Yin ,  Qiuxia Xu ,  Dapeng Chen

IPC分类号： H01L27/092 ,  H01L21/8238

CPC分类号： H01L27/092 ,  H01L21/76232 ,  H01L21/823807 ,  H01L29/165 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7834 ,  H01L29/7846 ,  H01L29/7848

摘要： The present invention provides a semiconductor structure, comprising: a substrate; a gate stack located on the substrate and comprising at least a gate dielectric layer and a gate electrode layer; source/drain regions, located in the substrate on both sides of the gate stack; an STI structure, located in the substrate on both sides of the source/drain regions, wherein the cross-section of the STI structure is trapezoidal, Sigma-shaped or inverted trapezoidal depending on the type of the semiconductor structure. Correspondingly, the present invention further to provides a method of manufacturing the semiconductor structure. In the present invention, STI structures having different shapes can be combined with different stress fillers to apply tensile stress or compressive stress laterally to the channel, which will produce a positive impact on the electron mobility of NMOS and the hole mobility of PMOS and increase the channel current of the device, thereby effectively improving the performance of the semiconductor structure.

摘要翻译： 本发明提供一种半导体结构，包括：基板; 位于所述基板上并且至少包括栅极电介质层和栅极电极层的栅极堆叠; 源极/漏极区域，位于栅极堆叠两侧的衬底中; STI结构，位于源极/漏极区两侧的衬底中，其中根据半导体结构的类型，STI结构的横截面为梯形，Σ形或倒梯形。 相应地，本发明还提供一种制造半导体结构的方法。 在本发明中，具有不同形状的STI结构可以与不同的应力填料组合以向沟道侧向施加拉伸应力或压应力，这将对NMOS的电子迁移率和PMOS的空穴迁移率产生积极影响，并增加 通道电流，从而有效地提高了半导体结构的性能。

公开(公告)号：US20130241004A1

公开(公告)日：2013-09-19

申请号：US13520618

申请日：2012-04-11

申请人： Huaxiang Yin ,  Zuozhen Fu ,  Qiuxia Xu ,  Chao Zhao ,  Dapeng Chen

发明人： Huaxiang Yin ,  Zuozhen Fu ,  Qiuxia Xu ,  Chao Zhao ,  Dapeng Chen

IPC分类号： H01L27/088 ,  H01L21/8236

CPC分类号： H01L21/823807 ,  H01L21/823842 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66545 ,  H01L29/7845

摘要： The present invention discloses a semiconductor device, comprising substrates, a plurality of gate stack structures on the substrate, a plurality of gate spacer structures on both sides of each gate stack structure, a plurality of source and drain regions in the substrate on both sides of each gate spacer structure, the plurality of gate spacer structures comprising a plurality of first gate stack structures and a plurality of second gate stack structures, wherein each of the first gate stack structures comprises a first gate insulating layer, a first work function metal layer, a second work function metal diffusion blocking layer, and a gate filling layer; Each of the second gate stack structures comprises a second gate insulating layer, a first work function metal layer, a second work function metal layer, and a gate filling layer, characterized in that the first work function metal layer has a first stress, and the gate filling layer has a second stress. Two metal gate layers of different types and/or intensity of stress are formed, respectively, thus different stresses are applied to the channel regions of different MOSFETs effectively and accurately, the device carrier mobility is enhanced simply and efficiently, and the device performance is also enhanced.

摘要翻译： 本发明公开了一种半导体器件，包括衬底，衬底上的多个栅极堆叠结构，在每个栅极堆叠结构的两侧上的多个栅极间隔结构，在衬底的两侧的多个源极和漏极区域 每个栅极间隔结构，所述多个栅极间隔结构包括多个第一栅极堆叠结构和多个第二栅极堆叠结构，其中所述第一栅极堆叠结构中的每一个包括第一栅极绝缘层，第一功函数金属层， 第二功函数金属扩散阻挡层和栅极填充层; 每个第二栅极堆叠结构包括第二栅极绝缘层，第一功函数金属层，第二功函数金属层和栅极填充层，其特征在于，第一功函数金属层具有第一应力，并且 栅极填充层具有第二应力。 形成不同类型和/或应力强度的两个金属栅极层，从而有效且准确地对不同MOSFET的沟道区域施加不同的应力，简单高效地提高器件载流子迁移率，器件性能也是 增强。

公开(公告)号：US09384986B2

公开(公告)日：2016-07-05

申请号：US14396845

申请日：2012-05-17

申请人： Huaxiang Yin ,  Zuozhen Fu ,  Qiuxia Xu ,  Dapeng Chen

发明人： Huaxiang Yin ,  Zuozhen Fu ,  Qiuxia Xu ,  Dapeng Chen

IPC分类号： H01L21/28 ,  H01L29/66 ,  H01L21/8238 ,  H01L21/8234 ,  H01L27/092 ,  H01L29/51

CPC分类号： H01L21/28088 ,  H01L21/28 ,  H01L21/28008 ,  H01L21/28026 ,  H01L21/28044 ,  H01L21/28079 ,  H01L21/82345 ,  H01L21/823842 ,  H01L27/092 ,  H01L27/0928 ,  H01L29/517 ,  H01L29/66515 ,  H01L29/66545

摘要： A method for manufacturing a dual metal CMOS device comprising: forming a first type metal work function modulation layer in the first gate trench and the second gate trench; forming a second type work function metal diffusion source layer in the first gate trench and the second gate trench; forming a heat isolation layer that shields the region of the first type device; and thermally annealing the regions where the first type device and the second type device are located.

摘要翻译： 一种用于制造双金属CMOS器件的方法，包括：在所述第一栅极沟槽和所述第二栅极沟槽中形成第一类型金属功函数调制层; 在所述第一栅极沟槽和所述第二栅极沟槽中形成第二类型功函数金属扩散源层; 形成屏蔽所述第一类型装置的区域的热隔离层; 并对第一类型器件和第二类型器件所在的区域进行热退火。