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    ESTABLISHING A SECURE MEMORY PATH IN A UNITARY MEMORY ARCHITECTURE
    1.
    发明申请
    ESTABLISHING A SECURE MEMORY PATH IN A UNITARY MEMORY ARCHITECTURE 有权
    在一个单一的存储器架构中建立安全的存储路径

    公开(公告)号：US20120023337A1

    公开(公告)日：2012-01-26

    申请号：US13139182

    申请日：2009-11-23

    申请人： Hugues De Perthuis ,  Stephane Mutz

    发明人： Hugues De Perthuis ,  Stephane Mutz

    IPC分类号： G06F12/14

    CPC分类号： G06F12/1466 ,  H04L9/0637

    摘要： A functional unit of a device is associated with a secret. Data stored in a memory location of the device is encrypted using the secret. The memory location of the device is accessible to other functional units; but without knowledge of the secret, the stored encrypted data is useless. The sharing of the secret creates a secure path between memory locations and functional units of the device while maintaining a unitary memory architecture. This abstract is not to be considered limiting, since other embodiments may deviate from the features described in this abstract.

    摘要翻译： 设备的功能单元与秘密相关联。 使用秘密对存储在设备的存储器位置的数据进行加密。 其他功能单元可访问设备的存储位置; 但是不知道秘密，存储的加密数据是无用的。 秘密的共享在设备的存储器位置和功能单元之间创建一个安全的路径，同时保持一体的存储架构。 该摘要不被认为是限制性的，因为其他实施例可能偏离本摘要中描述的特征。

    Establishing a secure memory path in a unitary memory architecture
    2.
    发明授权
    Establishing a secure memory path in a unitary memory architecture 有权
    在单一内存架构中建立安全的内存路径

    公开(公告)号：US08707054B2

    公开(公告)日：2014-04-22

    申请号：US13139182

    申请日：2009-11-23

    申请人： Hugues De Perthuis ,  Stephane Mutz

    发明人： Hugues De Perthuis ,  Stephane Mutz

    IPC分类号： G06F21/14 ,  H04L9/32 ,  G06F11/30 ,  G06F1/00 ,  H04L9/00

    CPC分类号： G06F12/1466 ,  H04L9/0637

    摘要： A functional unit of a device is associated with a secret. Data stored in a memory location of the device is encrypted using the secret. The memory location of the device is accessible to other functional units; but without knowledge of the secret, the stored encrypted data is useless. The sharing of the secret creates a secure path between memory locations and functional units of the device while maintaining a unitary memory architecture. This abstract is not to be considered limiting, since other embodiments may deviate from the features described in this abstract.

    摘要翻译： 设备的功能单元与秘密相关联。 使用秘密对存储在设备的存储器位置的数据进行加密。 其他功能单元可访问设备的存储位置; 但是不知道秘密，存储的加密数据是无用的。 秘密的共享在设备的存储器位置和功能单元之间创建一个安全的路径，同时保持一体的存储架构。 该摘要不被认为是限制性的，因为其他实施例可能偏离本摘要中描述的特征。

    Video processing device with low memory bandwidth requirements
    3.
    发明申请
    Video processing device with low memory bandwidth requirements 有权
    具有低内存带宽要求的视频处理设备

    公开(公告)号：US20070086522A1

    公开(公告)日：2007-04-19

    申请号：US10556616

    申请日：2004-05-06

    申请人： Stephane Mutz ,  Hugues De Perthuis ,  Eric Desmicht

    发明人： Stephane Mutz ,  Hugues De Perthuis ,  Eric Desmicht

    IPC分类号： H04N7/12 ,  H04N11/04

    CPC分类号： H04N19/433 ,  H04N19/44 ,  H04N19/51 ,  H04N19/61

    摘要： The present invention relates to a video processing device for processing data corresponding to a sequence of pictures according to a predictive block-based encoding technique. Said device comprises a processing unit (20) including a reconstruction circuit (16) for reconstructing pictures from decoded data and an external memory (1) for storing reference pictures delivered by the reconstruction circuit. The processing unit further comprises a memory controller (11) for controlling data exchange between the processing unit and the external memory, a cache memory (17) for temporarily storing data corresponding to a prediction area, said data being read out from the external memory via the memory controller, and a motion compensation circuit (14) for delivering motion compensated data to the reconstruction circuit on the basis of the prediction area read out from the cache memory.

    摘要翻译： 本发明涉及一种视频处理装置，用于根据预测的基于块的编码技术处理对应于图像序列的数据。 所述装置包括处理单元（20），该处理单元（20）包括用于从解码数据重建图像的重构电路（16）和用于存储由重建电路传送的参考图像的外部存储器（1）。 处理单元还包括用于控制处理单元和外部存储器之间的数据交换的存储器控​​制器（11），用于临时存储对应于预测区域的数据的高速缓冲存储器（17），所述数据从外部存储器经由 存储器控制器和用于基于从高速缓冲存储器读出的预测区域将运动补偿数据传送到重建电路的运动补偿电路（14）。

    Access to a common memory in which a priority access to a non-active bank is prepared during a non-priority access to a different bank
    4.
    发明授权
    Access to a common memory in which a priority access to a non-active bank is prepared during a non-priority access to a different bank 有权
    在对不同银行进行非优先访问期间，可以访问其中准备对非活动银行的优先访问的公共存储器

    公开(公告)号：US07038964B2

    公开(公告)日：2006-05-02

    申请号：US10478559

    申请日：2002-05-21

    申请人： Stephane Mutz ,  Hugues De Perthuis ,  Thierry Gourbilleau

    发明人： Stephane Mutz ,  Hugues De Perthuis ,  Thierry Gourbilleau

    IPC分类号： G06F13/14 ,  G11C7/00

    CPC分类号： G06F13/18 ,  G06F13/1647

    摘要： Access of multiple data processing circuits to a common memory having several banks is managed, the memory being connected to one or several circuits for processing ordinary data and to a circuit for processing priority data. A method of managing access includes producing an access demand of a circuit for processing ordinary data to a bank of the memory, starting the realization of the demanded access, subsequently producing an access demand of the circuit for processing priority data to another bank of the memory, preparing, during the realization of the access demanded by the ordinary data processing circuits, the other bank of the memory, and interrupting the access in the course of realization as soon as said preparation is completed.

    摘要翻译： 管理多个数据处理电路到具有多个存储体的公共存储器的存取，存储器被连接到一个或多个用于处理普通数据的电路和用于处理优先级数据的电路。 管理访问的方法包括产生用于将普通数据处理到存储器的存储器的电路的访问需求，开始实现所请求的访问，随后产生用于将优先权数据处理到存储器的另一存储体的电路的访问需求 在实现普通数据处理电路所要求的接入的同时，准备好另一个存储器，并且在所述准备完成之后中断实现过程中的接入。

    Access to a collective resource in which low priority functions are grouped, read accesses of the group being given higher priority than write accesses of the group
    5.
    发明授权
    Access to a collective resource in which low priority functions are grouped, read accesses of the group being given higher priority than write accesses of the group 有权
    访问低优先级功能被分组的集合资源，组的读访问被给予比组的写访问更高的优先级

    公开(公告)号：US07689781B2

    公开(公告)日：2010-03-30

    申请号：US10372545

    申请日：2003-02-24

    申请人： Hugues De Perthuis ,  Eric Desmicht

    发明人： Hugues De Perthuis ,  Eric Desmicht

    IPC分类号： G06F12/00

    CPC分类号： G06F13/18

    摘要： The invention relates to a functional system comprising a set of functions (F, F′) which are to access a collective resource (RSRC), the system including an interface (INT) arranged to implement an access scheme (AS) including at least one state (I) defined by an order of priority for an arbitration according to which the functions (F, F′) can access the collective resource (RSRC), the state (I) being characterized in that, for at least one set of at least two functions (F), the access possibilities in read mode (F_R) and the access possibilities in write mode (F_W) have different priority levels, the access possibilities in read mode having consecutive priority levels higher than the priority levels of the access possibilities in write mode.

    摘要翻译： 本发明涉及一种包括一组功能（F，F'）的功能系统，其功能是要访问集体资源（RSRC），所述系统包括布置成实现包括至少一个的接入方案（AS）的接口（INT） 状态（I）由仲裁的优先顺序定义，根据该顺序，功能（F，F'）可以访问集体资源（RSRC），状态（I）的特征在于，对于至少一组在 至少两个功能（F），读取模式（F_R）的访问可能性和写入模式（F_W）中的访问可能性具有不同的优先级，读取模式下的访问可能性具有比访问可能性的优先级更高的连续优先级 在写入模式。

    Video processing device with low memory bandwidth requirements
    6.
    发明授权
    Video processing device with low memory bandwidth requirements 有权
    具有低内存带宽要求的视频处理设备

    公开(公告)号：US08155459B2

    公开(公告)日：2012-04-10

    申请号：US10556616

    申请日：2004-05-06

    申请人： Stéphane Mutz ,  Hugues De Perthuis ,  Eric Desmicht

    发明人： Stéphane Mutz ,  Hugues De Perthuis ,  Eric Desmicht

    IPC分类号： G06K9/36 ,  H04N7/12

    CPC分类号： H04N19/433 ,  H04N19/44 ,  H04N19/51 ,  H04N19/61

    摘要： The present invention relates to a video processing device for processing data corresponding to a sequence of pictures according to a predictive block-based encoding technique. Said device comprises a processing unit (20) including a reconstruction circuit (16) for reconstructing pictures from decoded data and an external memory (1) for storing reference pictures delivered by the reconstruction circuit. The processing unit further comprises a memory controller (11) for controlling data exchange between the processing unit and the external memory, a cache memory (17) for temporarily storing data corresponding to a prediction area, said data being read out from the external memory via the memory controller, and a motion compensation circuit (14) for delivering motion compensated data to the reconstruction circuit on the basis of the prediction area read out from the cache memory.

    摘要翻译： 本发明涉及一种视频处理装置，用于根据预测的基于块的编码技术处理对应于图像序列的数据。 所述装置包括处理单元（20），该处理单元（20）包括用于从解码数据重建图像的重构电路（16）和用于存储由重建电路传送的参考图像的外部存储器（1）。 处理单元还包括用于控制处理单元和外部存储器之间的数据交换的存储器控​​制器（11），用于临时存储对应于预测区域的数据的高速缓冲存储器（17），所述数据从外部存储器经由 存储器控制器和用于基于从高速缓冲存储器读出的预测区域将运动补偿数据传送到重建电路的运动补偿电路（14）。

    Optimized detection of a watermark in an information signal
    7.
    发明授权
    Optimized detection of a watermark in an information signal 有权

    公开(公告)号：US07110567B2

    公开(公告)日：2006-09-19

    申请号：US10321199

    申请日：2002-12-17

    申请人： Hugues De Perthuis ,  Eric Desmicht

    发明人： Hugues De Perthuis ,  Eric Desmicht

    IPC分类号： G06K9/00

    CPC分类号： H04N1/32154 ,  G06T1/0021 ,  G06T2200/28 ,  G06T2201/0052 ,  G06T2201/0065 ,  H04N1/00037 ,  H04N1/3216 ,  H04N2201/3233 ,  H04N2201/327

    摘要： The invention relates to a method of detecting a watermark W, formed by a set of coefficients, in an information signal S, said watermark W and said information signal S being configured in the form of matrices SM M*M. The coefficients of the Fourier transform matrix of the matrix of the signal TSM and the coefficients of the Fourier transform matrix of the watermark matrix TWM are used in a calculation step CAL of the inverse transform matrix of the multiplication ITM of the transform matrix of the signal TSM and of the transform matrix of the watermark TWM, said calculation CAL being produced in sequences which each result in obtaining I columns of the inverse transform matrix of the multiplication, where M is a multiple of I and different from I. Said I columns are stored in a memory called internal memory and the detection step DET of the watermark is achieved with each sequence by detection of peaks of each set of the I columns while said I columns are present in the internal memory. The invention permits the use of a small-size internal memory.

    Data processing device for use in cooperation with a memory
    8.
    发明授权
    Data processing device for use in cooperation with a memory 有权
    与存储器配合使用的数据处理装置

    公开(公告)号：US06785795B1

    公开(公告)日：2004-08-31

    申请号：US09649940

    申请日：2000-08-29

    申请人： Hugues De Perthuis ,  Thierry Nouvet

    发明人： Hugues De Perthuis ,  Thierry Nouvet

    IPC分类号： G06F1200

    CPC分类号： G06F13/1663 ,  G06F13/1605 ,  G06F13/1668 ,  Y10S707/99936

    摘要： A processing of data in cooperation with a memory (MEM), for example an MPEG decoding, has the following characteristic features. A processor (P) generates a logic request (LRQ). The logic request (LRQ) defines at least one characteristic (CAR) common to a group of data (GRP). An addressing circuit (AGA) generates a physical request (PRQ) on the basis of the logic request (LRQ). The physical request (PRQ) defines memory (MEM) addresses (A) relating to the group of data (GRP). A memory interface (INT) effects a transfer (TRNSFR) of the group of data (GRP) between the memory (MEM) and the processor (P) on the basis of the physical request (PRQ). Thus, the processor need not know how and where the data to be processed or having been processed are stored in the memory. This facilitates the design of a data processing device and, particularly, a family of such devices.

    摘要翻译： 与存储器（MEM）协作的数据处理，例如MPEG解码，具有以下特征。 处理器（P）产生逻辑请求（LRQ）。 逻辑请求（LRQ）定义了一组数据（GRP）共有的至少一个特征（CAR）。 寻址电路（AGA）根据逻辑请求（LRQ）生成物理请求（PRQ）。 物理请求（PRQ）定义与数据组（GRP）相关的存储器（MEM）地址（A）。 存储器接口（INT）根据物理请求（PRQ）实现存储器（MEM）和处理器（P）之间的数据组（GRP）的传输（TRNSFR）。 因此，处理器不需要知道如何以及在哪里处理或被处理的数据被存储在存储器中。 这有助于数据处理设备的设计，特别是这样的设备的系列。

    Dynamic access control of a function to a collective resource
    9.
    发明授权
    Dynamic access control of a function to a collective resource 有权
    功能对集体资源的动态访问控制

    公开(公告)号：US06959371B2

    公开(公告)日：2005-10-25

    申请号：US10228442

    申请日：2002-08-27

    申请人： Hugues De Perthuis ,  Eric Desmicht

    发明人： Hugues De Perthuis ,  Eric Desmicht

    IPC分类号： G06F12/00 ,  G06F13/16 ,  G06F13/36 ,  G06F13/362

    CPC分类号： G06F13/362 ,  G06F13/1605

    摘要： Access by a function to a collective resource is controlled by requiring that the function waits for a minimum number of clock cycles CLK called latency [LAT] between two successive accesses of the function. The function is further required to wait a number of cycles called penalty [PEN] which is higher than the latency between two successive accesses when a given number of successive accesses separated in time by at least the value of the latency has taken place beforehand. Registers [REG1, REG2] are decremented (or incremented) with each clock cycle and incremented (or decremented) with each access of the function to the collective resource. Tests [T1, T3, T4] are made with the contents of the registers to authorize [GRT] the access to the collective resource.

    摘要翻译： 通过要求功能等待在功能的两次连续访问之间被称为延迟[LAT]的最小数量的时钟周期CLK来控制由功能到集体资源的访问。 该功能还需要等待多个周期，称为罚款[PEN]，当在时间上至少等待时间间隔已经发生的给定次数的连续访问事先已经发生时，该次数高于两次连续访问之间的等待时间。 寄存器[REG 1，REG 2]随着每个时钟周期递减（或递增），并且随着函数的每次访问到集合资源而递增（或递减）。 测试[T 1，T 3，T 4]由登记册的内容作出，授权[GRT]访问集体资源。

    Arrangement with a plurality of processors having an interface for a collective memory
    10.
    发明授权
    Arrangement with a plurality of processors having an interface for a collective memory 有权
    具有用于集体存储器的接口的多个处理器的布置

    公开(公告)号：US06738840B1

    公开(公告)日：2004-05-18

    申请号：US09640734

    申请日：2000-08-17

    申请人： Thierry Nouvet ,  Hugues De Perthuis ,  Stéphane Mutz

    发明人： Thierry Nouvet ,  Hugues De Perthuis ,  Stéphane Mutz

    IPC分类号： G06F300

    CPC分类号： G06F13/1605 ,  G06F13/1663 ,  G06F13/1668

    摘要： A data processing arrangement comprises a plurality of processors and a memory interface via which the processors can access a collective memory. The memory interface comprises an interface memory (SRAM) for temporarily storing data belonging to different processors. The memory interface also comprises a control circuit for controlling the interface memory in such a manner that it forms a FIFO memory for each of the different processors. This makes to possible to realize implementations at a comparatively low cost in comparison with a memory interface comprising a separate FIFO memory for each processor.

    摘要翻译： 数据处理装置包括多个处理器和存储器接口，处理器可以经由该存储器接口访问集体存储器。 存储器接口包括用于临时存储属于不同处理器的数据的接口存储器（SRAM）。 存储器接口还包括用于以这样的方式控制接口存储器的控制电路，即它为每个不同处理器形成FIFO存储器。 与包括用于每个处理器的单独的FIFO存储器的存储器接口相比，这使得可以以相对低的成本实现实现。