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1.发明授权Self-forming, self-aligned barriers for back-end interconnects and methods of making same 有权用于后端互连的自成型，自对准屏障及其制造方法公开(公告)号：US08461683B2
公开(公告)日：2013-06-11
申请号：US13078683
申请日：2011-04-01
IPC分类号： H01L23/52 , H01L23/48 , H01L29/40 , H01L23/485
CPC分类号： H01L21/76834 , H01L21/2855 , H01L21/32053 , H01L21/76832 , H01L21/76835 , H01L21/76843 , H01L21/76846 , H01L21/76849 , H01L21/76855 , H01L21/76864 , H01L21/76867 , H01L21/76897 , H01L23/485 , H01L23/53223 , H01L23/53238 , H01L23/53266 , H01L2924/0002 , Y10S438/927 , H01L2924/00
摘要： Processes of forming an insulated wire into an interlayer dielectric layer (ILD) of a back-end metallization includes thermally treating a metallic barrier precursor under conditions to cause at least one alloying element in the barrier precursor to form a dielectric barrier between the wire and the ILD. The dielectric barrier is therefore a self-forming, self-aligned barrier. Thermal processing is done under conditions to cause the at least one alloying element to migrate from a zone of higher concentration thereof to a zone of lower concentration thereof to further form the dielectric barrier. Various apparatus are made by the process.
摘要翻译： 在后端金属化的层间电介质层（ILD）中形成绝缘线的工艺包括在使阻挡前体中的至少一个合金元素引起的金属屏障前体之间形成电介质势垒 ILD。 因此，介电阻挡层是自形成的自对准势垒。 热处理在使至少一种合金元素从其较高浓度的区域迁移到其较低浓度的区域的条件下进行以进一步形成电介质阻挡层。 通过该方法制造各种装置。
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2.发明申请SELF-FORMING, SELF-ALIGNED BARRIERS FOR BACK-END INTERCONNECTS AND METHODS OF MAKING SAME 有权自成型，后端互连的自对准障碍及其制造方法公开(公告)号：US20120248608A1
公开(公告)日：2012-10-04
申请号：US13078683
申请日：2011-04-01
IPC分类号： H01L23/485 , H01L21/768
CPC分类号： H01L21/76834 , H01L21/2855 , H01L21/32053 , H01L21/76832 , H01L21/76835 , H01L21/76843 , H01L21/76846 , H01L21/76849 , H01L21/76855 , H01L21/76864 , H01L21/76867 , H01L21/76897 , H01L23/485 , H01L23/53223 , H01L23/53238 , H01L23/53266 , H01L2924/0002 , Y10S438/927 , H01L2924/00
摘要： Processes of forming an insulated wire into an interlayer dielectric layer (ILD) of a back-end metallization includes thermally treating a metallic barrier precursor under conditions to cause at least one alloying element in the barrier precursor to form a dielectric barrier between the wire and the ILD. The dielectric barrier is therefore a self-forming, self-aligned barrier. Thermal processing is done under conditions to cause the at least one alloying element to migrate from a zone of higher concentration thereof to a zone of lower concentration thereof to further form the dielectric barrier. Various apparatus are made by the process.
摘要翻译： 在后端金属化的层间电介质层（ILD）中形成绝缘线的工艺包括在使阻挡前体中的至少一个合金元素引起的金属屏障前体之间形成电介质势垒 ILD。 因此，介电阻挡层是自形成的自对准势垒。 热处理在使至少一种合金元素从其较高浓度的区域迁移到其较低浓度的区域的条件下进行以进一步形成电介质阻挡层。 通过该方法制造各种装置。
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3.发明申请SELF-FORMING, SELF-ALIGNED BARRIERS FOR BACK-END INTERCONNECTS AND METHODS OF MAKING SAME 审中-公开自成型，后端互连的自对准障碍及其制造方法公开(公告)号：US20130260553A1
公开(公告)日：2013-10-03
申请号：US13893143
申请日：2013-05-13
IPC分类号： H01L21/768
CPC分类号： H01L21/76834 , H01L21/2855 , H01L21/32053 , H01L21/76832 , H01L21/76835 , H01L21/76843 , H01L21/76846 , H01L21/76849 , H01L21/76855 , H01L21/76864 , H01L21/76867 , H01L21/76897 , H01L23/485 , H01L23/53223 , H01L23/53238 , H01L23/53266 , H01L2924/0002 , Y10S438/927 , H01L2924/00
摘要： Processes of forming an insulated wire into an interlayer dielectric layer (ILD) of a back-end metallization includes thermally treating a metallic barrier precursor under conditions to cause at least one alloying element in the barrier precursor to form a dielectric barrier between the wire and the ILD. The dielectric barrier is therefore a self-forming, self-aligned barrier. Thermal processing is done under conditions to cause the at least one alloying element to migrate from a zone of higher concentration thereof to a zone of lower concentration thereof to further form the dielectric barrier. Various apparatus are made by the process.
摘要翻译： 在后端金属化的层间电介质层（ILD）中形成绝缘线的工艺包括在使阻挡前体中的至少一个合金元素引起的金属屏障前体之间形成电介质势垒 ILD。 因此，介电阻挡层是自形成的自对准势垒。 热处理在使至少一种合金元素从其较高浓度的区域迁移到其较低浓度的区域的条件下进行以进一步形成电介质阻挡层。 通过该方法制造各种装置。
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4.发明授权Methods for forming planarized hermetic barrier layers and structures formed thereby 有权用于形成平坦化的气密屏障层及由此形成的结构的方法公开(公告)号：US08039920B1
公开(公告)日：2011-10-18
申请号：US12948410
申请日：2010-11-17
申请人： Sean W. King , Hui Jae Yoo
发明人： Sean W. King , Hui Jae Yoo
IPC分类号： H01L21/00
CPC分类号： H02J7/0045 , H01L21/76829 , H01L21/76832 , H01L21/76834 , H01L21/76837 , H01L21/76849 , H01L21/76867 , H01L21/76883
摘要： Methods and associated structures of forming a microelectronic structure are described. Those methods may comprise forming a conductive material in an interconnect opening within an interlayer dielectric material that is disposed on a substrate, forming a low density dielectric material on a surface of the dielectric layer and on a surface of the conductive material, and forming a high density dielectric barrier layer on the low density dielectric layer.
摘要翻译： 描述了形成微电子结构的方法和相关结构。 这些方法可以包括在布置在基板上的层间电介质材料中的互连开口中形成导电材料，在电介质层的表面和导电材料的表面上形成低密度电介质材料，并形成高 密度介电阻挡层在低密度电介质层上。
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5.发明申请METHODS FOR FORMING PLANARIZED HERMETIC BARRIER LAYERS AND STRUCTURES FORMED THEREBY 有权形成平面化掩膜层的方法及其形成的结构公开(公告)号：US20120122312A1
公开(公告)日：2012-05-17
申请号：US13276062
申请日：2011-10-18
申请人： Sean W. King , Hui Jae Yoo
发明人： Sean W. King , Hui Jae Yoo
IPC分类号： H01L21/768 , H01L21/31
CPC分类号： H02J7/0045 , H01L21/76829 , H01L21/76832 , H01L21/76834 , H01L21/76837 , H01L21/76849 , H01L21/76867 , H01L21/76883
摘要： Methods and associated structures of forming a microelectronic structure are described. Those methods may comprise forming a conductive material in an interconnect opening within an interlayer dielectric material that is disposed on a substrate, forming a low density dielectric material on a surface of the dielectric layer and on a surface of the conductive material, and forming a high density dielectric barrier layer on the low density dielectric layer.
摘要翻译： 描述了形成微电子结构的方法和相关结构。 这些方法可以包括在布置在基板上的层间电介质材料中的互连开口中形成导电材料，在电介质层的表面和导电材料的表面上形成低密度电介质材料，并形成高 密度介电阻挡层在低密度电介质层上。
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6.发明授权Methods for forming planarized hermetic barrier layers and structures formed thereby 有权用于形成平坦化的气密屏障层及由此形成的结构的方法公开(公告)号：US08524597B2
公开(公告)日：2013-09-03
申请号：US13276062
申请日：2011-10-18
申请人： Sean W. King , Hui Jae Yoo
发明人： Sean W. King , Hui Jae Yoo
IPC分类号： H01L21/4763
CPC分类号： H02J7/0045 , H01L21/76829 , H01L21/76832 , H01L21/76834 , H01L21/76837 , H01L21/76849 , H01L21/76867 , H01L21/76883
摘要： Methods and associated structures of forming a microelectronic structure are described. Those methods may comprise forming a conductive material in an interconnect opening within an interlayer dielectric material that is disposed on a substrate, forming a low density dielectric material on a surface of the dielectric layer and on a surface of the conductive material, and forming a high density dielectric barrier layer on the low density dielectric layer.
摘要翻译： 描述了形成微电子结构的方法和相关结构。 这些方法可以包括在布置在基板上的层间电介质材料中的互连开口中形成导电材料，在电介质层的表面和导电材料的表面上形成低密度电介质材料，并形成高 密度介电阻挡层在低密度电介质层上。
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7.发明授权Multi-layer film stack for extinction of substrate reflections during patterning 有权在图案化期间用于消除衬底反射的多层膜堆叠公开(公告)号：US07291552B2
公开(公告)日：2007-11-06
申请号：US11300023
申请日：2005-12-13
IPC分类号： H01L21/4763
CPC分类号： H01L21/31144 , H01L21/0276 , H01L21/76802 , H01L21/76832 , H01L23/53295 , H01L2924/0002 , Y10S438/902 , Y10S438/945 , Y10S438/95 , Y10S438/952 , Y10S438/958 , H01L2924/00
摘要： A method including introducing a dielectric layer over a substrate between an interconnection line and the substrate, the dielectric layer comprising a plurality of alternating material layers; and patterning an interconnection to the substrate. An apparatus comprising a substrate comprising a plurality of devices formed thereon; and an interlayer dielectric layer comprising a base layer and a cap layer, the cap layer comprising a plurality of alternating material layers overlying the substrate.
摘要翻译： 一种方法，包括在互连线和衬底之间的衬底上引入电介质层，所述电介质层包括多个交替材料层; 并且图案化到衬底的互连。 一种包括其上形成有多个装置的基板的装置; 以及包括基层和盖层的层间介电层，所述盖层包括覆盖在所述基板上的多个交替材料层。
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公开(公告)号：US06974772B1
公开(公告)日：2005-12-13
申请号：US10922619
申请日：2004-08-19
申请人： Sean W. King , Andrew W. Ott
发明人： Sean W. King , Andrew W. Ott
IPC分类号： H01L21/4763 , H01L21/768 , H01L23/532
CPC分类号： H01L23/53295 , H01L21/76802 , H01L21/76807 , H01L21/76829 , H01L21/76849 , H01L2924/0002 , H01L2924/00
摘要： Embodiments of the invention provide a device with a hard mask layer between first and second ILD layers. The hard mask layer may have a k value approximately equal to the first and/or second ILD layers.
摘要翻译： 本发明的实施例提供一种在第一和第二ILD层之间具有硬掩模层的装置。 硬掩模层可以具有近似等于第一和/或第二ILD层的k值。
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公开(公告)号：US07172960B2
公开(公告)日：2007-02-06
申请号：US09750734
申请日：2000-12-27
IPC分类号： H01L21/4763 , H01L21/461 , H01L21/302 , H01L21/469
CPC分类号： H01L21/31144 , H01L21/0276 , H01L21/76802 , H01L21/76832 , H01L23/53295 , H01L2924/0002 , Y10S438/902 , Y10S438/945 , Y10S438/95 , Y10S438/952 , Y10S438/958 , H01L2924/00
摘要： A method including introducing a dielectric layer over a substrate between an interconnection line and the substrate, the dielectric layer comprising a plurality of alternating material layers; and patterning an interconnection to the substrate. An apparatus comprising a substrate comprising a plurality of devices formed thereon; and an interlayer dielectric layer comprising a base layer and a cap layer, the cap layer comprising a plurality of alternating material layers overlying the substrate.
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公开(公告)号：US07199473B2
公开(公告)日：2007-04-03
申请号：US11028884
申请日：2005-01-03
申请人： Sean W. King , Andrew W. Ott
发明人： Sean W. King , Andrew W. Ott
CPC分类号： H01L23/53295 , H01L21/76802 , H01L21/76807 , H01L21/76829 , H01L21/76849 , H01L2924/0002 , H01L2924/00
摘要： Embodiments of the invention provide a device with a hard mask layer between first and second ILD layers. The hard mask layer may have a k value approximately equal to the first and/or second ILD layers.
摘要翻译： 本发明的实施例提供一种在第一和第二ILD层之间具有硬掩模层的装置。 硬掩模层可以具有近似等于第一和/或第二ILD层的k值。
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