公开(公告)号：US08975138B2

公开(公告)日：2015-03-10

申请号：US13931219

申请日：2013-06-28

Applicant: Manish Chandhok ,  Hui Jae Yoo ,  Yan A. Borodovsky ,  Florian Gstrein ,  David N. Shykind ,  Kevin L. Lin

Inventor： Manish Chandhok ,  Hui Jae Yoo ,  Yan A. Borodovsky ,  Florian Gstrein ,  David N. Shykind ,  Kevin L. Lin

IPC: H01L21/336 ,  H01L21/461 ,  H01L21/8234 ,  H01L23/535 ,  H01L21/768

CPC classification number: H01L23/5226 ,  H01L21/32133 ,  H01L21/32139 ,  H01L21/76802 ,  H01L21/7682 ,  H01L21/76877 ,  H01L21/76879 ,  H01L21/76883 ,  H01L21/76885 ,  H01L21/76886 ,  H01L21/76897 ,  H01L23/5222 ,  H01L23/528 ,  H01L23/53209 ,  H01L23/53271 ,  H01L23/5329 ,  H01L23/53295 ,  H01L23/535 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method including patterning a thickness dimension of an interconnect material into a thickness dimension for a wiring line with one or more vias extending from the wiring line and introducing a dielectric material on the interconnect material. A method including depositing and patterning an interconnect material into a wiring line and one or more vias; and introducing a dielectric material on the interconnect material such that the one or more vias are exposed through the dielectric material. An apparatus including a first interconnect layer in a first plane and a second interconnect in a second plane on a substrate; and a dielectric layer separating the first and second interconnect layers, wherein the first interconnect layer comprises a monolith including a wiring line and at least one via, the at least one via extending from the wiring line to a wiring line of the second interconnect layer.

Abstract translation: 一种方法，包括将互连材料的厚度尺寸图案化为具有从布线延伸的一个或多个通孔的布线的厚度尺寸，并将介电材料引入到互连材料上。 一种包括将互连材料沉积和图案化成布线和一个或多个通孔的方法; 以及在所述互连材料上引入介电材料，使得所述一个或多个通孔通过所述介电材料暴露。 一种装置，包括在第一平面中的第一互连层和在衬底上的第二平面中的第二互连; 以及分离所述第一和第二互连层的电介质层，其中所述第一互连层包括包括布线和至少一个通孔的整体，所述至少一个通孔从所述布线延伸到所述第二互连层的布线。

公开(公告)号：US08461683B2

公开(公告)日：2013-06-11

申请号：US13078683

申请日：2011-04-01

Applicant: Hui Jae Yoo ,  Jeffery D. Bielefeld ,  Sean W. King ,  Sridhar Balakrishnan

Inventor： Hui Jae Yoo ,  Jeffery D. Bielefeld ,  Sean W. King ,  Sridhar Balakrishnan

IPC: H01L23/52 ,  H01L23/48 ,  H01L29/40 ,  H01L23/485

CPC classification number: H01L21/76834 ,  H01L21/2855 ,  H01L21/32053 ,  H01L21/76832 ,  H01L21/76835 ,  H01L21/76843 ,  H01L21/76846 ,  H01L21/76849 ,  H01L21/76855 ,  H01L21/76864 ,  H01L21/76867 ,  H01L21/76897 ,  H01L23/485 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53266 ,  H01L2924/0002 ,  Y10S438/927 ,  H01L2924/00

Abstract: Processes of forming an insulated wire into an interlayer dielectric layer (ILD) of a back-end metallization includes thermally treating a metallic barrier precursor under conditions to cause at least one alloying element in the barrier precursor to form a dielectric barrier between the wire and the ILD. The dielectric barrier is therefore a self-forming, self-aligned barrier. Thermal processing is done under conditions to cause the at least one alloying element to migrate from a zone of higher concentration thereof to a zone of lower concentration thereof to further form the dielectric barrier. Various apparatus are made by the process.

Abstract translation: 在后端金属化的层间电介质层（ILD）中形成绝缘线的工艺包括在使阻挡前体中的至少一个合金元素引起的金属屏障前体之间形成电介质势垒 ILD。 因此，介电阻挡层是自形成的自对准势垒。 热处理在使至少一种合金元素从其较高浓度的区域迁移到其较低浓度的区域的条件下进行以进一步形成电介质阻挡层。 通过该方法制造各种装置。

公开(公告)号：US20120122312A1

公开(公告)日：2012-05-17

申请号：US13276062

申请日：2011-10-18

Applicant: Sean W. King ,  Hui Jae Yoo

Inventor： Sean W. King ,  Hui Jae Yoo

IPC: H01L21/768 ,  H01L21/31

CPC classification number: H02J7/0045 ,  H01L21/76829 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76837 ,  H01L21/76849 ,  H01L21/76867 ,  H01L21/76883

Abstract: Methods and associated structures of forming a microelectronic structure are described. Those methods may comprise forming a conductive material in an interconnect opening within an interlayer dielectric material that is disposed on a substrate, forming a low density dielectric material on a surface of the dielectric layer and on a surface of the conductive material, and forming a high density dielectric barrier layer on the low density dielectric layer.

Abstract translation: 描述了形成微电子结构的方法和相关结构。 这些方法可以包括在布置在基板上的层间电介质材料中的互连开口中形成导电材料，在电介质层的表面和导电材料的表面上形成低密度电介质材料，并形成高 密度介电阻挡层在低密度电介质层上。

公开(公告)号：US09330963B2

公开(公告)日：2016-05-03

申请号：US13976835

申请日：2011-12-20

Applicant: Sean King ,  Hui Jae Yoo ,  Sreenivas Kosaraju ,  Timothy Glassman

Inventor： Sean King ,  Hui Jae Yoo ,  Sreenivas Kosaraju ,  Timothy Glassman

IPC: H01L29/40 ,  H01L23/52 ,  H01L21/768 ,  H01L21/02 ,  H01L23/522 ,  H01L23/532

CPC classification number: H01L21/76831 ,  H01L21/02178 ,  H01L21/022 ,  H01L21/0228 ,  H01L21/76802 ,  H01L21/7682 ,  H01L21/76829 ,  H01L21/76877 ,  H01L23/522 ,  H01L23/5222 ,  H01L23/5226 ,  H01L23/53228 ,  H01L23/53295 ,  H01L23/564 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Conformal hermetic dielectric films suitable as dielectric diffusion barriers over 3D topography. In embodiments, the dielectric diffusion barrier includes a dielectric layer, such as a metal oxide, which can be deposited by atomic layer deposition (ALD) techniques with a conformality and density greater than can be achieved in a conventional silicon dioxide-based film deposited by a PECVD process for a thinner contiguous hermetic diffusion barrier. In further embodiments, the diffusion barrier is a multi-layered film including a high-k dielectric layer and a low-k or intermediate-k dielectric layer (e.g., a bi-layer) to reduce the dielectric constant of the diffusion barrier. In other embodiments a silicate of a high-k dielectric layer (e.g., a metal silicate) is formed to lower the k-value of the diffusion barrier by adjusting the silicon content of the silicate while maintaining high film conformality and density.

Abstract translation: 适合于3D地形的电介质扩散屏障的保形密封电介质膜。 在实施例中，电介质扩散阻挡层包括介电层，例如金属氧化物，其可以通过原子层沉积（ALD）技术沉积，其共形度和密度大于常规的基于二氧化硅的膜沉积的二氧化硅基膜 用于较薄连续密封扩散屏障的PECVD工艺。 在另外的实施例中，扩散阻挡层是包括高k电介质层和低k或中间介电层（例如双层）的多层膜，以降低扩散阻挡层的介电常数。 在其它实施方案中，形成高k电介质层（例如金属硅酸盐）的硅酸盐，以通过调节硅酸盐的硅含量来降低扩散阻挡层的k值，同时保持高的膜保形性和密度。

公开(公告)号：US20150091175A1

公开(公告)日：2015-04-02

申请号：US14039893

申请日：2013-09-27

Applicant: MANISH CHANDHOK ,  HUI JAE YOO ,  CHRISTOPHER JEZEWSKI ,  RAMANAN V. CHEBIAM ,  COLIN T. CARVER

Inventor： MANISH CHANDHOK ,  HUI JAE YOO ,  CHRISTOPHER JEZEWSKI ,  RAMANAN V. CHEBIAM ,  COLIN T. CARVER

IPC: H01L23/535 ,  H01L21/768

CPC classification number: H01L23/53238 ,  H01L21/7682 ,  H01L21/76841 ,  H01L21/76843 ,  H01L21/76849 ,  H01L21/76882 ,  H01L21/76883 ,  H01L23/5222 ,  H01L23/5283 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A metallization layer including a fully clad interconnect and a method of forming a fully clad interconnect. An opening is formed in a dielectric layer, wherein the dielectric layer has a surface and the opening includes walls and a bottom. A diffusion barrier layer and an adhesion layer are deposited on the dielectric layer. An interconnect material is deposited on the dielectric layer and reflowed into the opening forming an interconnect. An adhesion capping layer and diffusion barrier capping layer are deposited over the interconnect. The interconnect is surrounded by the adhesion layer and the adhesion capping layer and the adhesion layer and the adhesion capping layer are surrounded by the diffusion barrier layer and the diffusion capping layer.

Abstract translation: 包括全覆层互连的金属化层和形成完全包层的互连的方法。 在电介质层中形成开口，其中介电层具有表面，并且开口包括壁和底部。 扩散阻挡层和粘合层沉积在介电层上。 互连材料沉积在介电层上并回流到形成互连的开口中。 在互连上沉积粘合覆盖层和扩散阻挡覆盖层。 互连被粘合层和粘合覆盖层包围，粘合层和粘合覆盖层被扩散阻挡层和扩散覆盖层包围。

公开(公告)号：US08524597B2

公开(公告)日：2013-09-03

申请号：US13276062

申请日：2011-10-18

Applicant: Sean W. King ,  Hui Jae Yoo

Inventor： Sean W. King ,  Hui Jae Yoo

IPC: H01L21/4763

CPC classification number: H02J7/0045 ,  H01L21/76829 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76837 ,  H01L21/76849 ,  H01L21/76867 ,  H01L21/76883

Abstract: Methods and associated structures of forming a microelectronic structure are described. Those methods may comprise forming a conductive material in an interconnect opening within an interlayer dielectric material that is disposed on a substrate, forming a low density dielectric material on a surface of the dielectric layer and on a surface of the conductive material, and forming a high density dielectric barrier layer on the low density dielectric layer.

Abstract translation: 描述了形成微电子结构的方法和相关结构。 这些方法可以包括在布置在基板上的层间电介质材料中的互连开口中形成导电材料，在电介质层的表面和导电材料的表面上形成低密度电介质材料，并形成高 密度介电阻挡层在低密度电介质层上。

公开(公告)号：US20120248608A1

公开(公告)日：2012-10-04

申请号：US13078683

申请日：2011-04-01

Applicant: Hui Jae Yoo ,  Jeffery D. Bielefeld ,  Sean W. King ,  Sridhar Balakrishnan

Inventor： Hui Jae Yoo ,  Jeffery D. Bielefeld ,  Sean W. King ,  Sridhar Balakrishnan

IPC: H01L23/485 ,  H01L21/768

CPC classification number: H01L21/76834 ,  H01L21/2855 ,  H01L21/32053 ,  H01L21/76832 ,  H01L21/76835 ,  H01L21/76843 ,  H01L21/76846 ,  H01L21/76849 ,  H01L21/76855 ,  H01L21/76864 ,  H01L21/76867 ,  H01L21/76897 ,  H01L23/485 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53266 ,  H01L2924/0002 ,  Y10S438/927 ,  H01L2924/00

Abstract: Processes of forming an insulated wire into an interlayer dielectric layer (ILD) of a back-end metallization includes thermally treating a metallic barrier precursor under conditions to cause at least one alloying element in the barrier precursor to form a dielectric barrier between the wire and the ILD. The dielectric barrier is therefore a self-forming, self-aligned barrier. Thermal processing is done under conditions to cause the at least one alloying element to migrate from a zone of higher concentration thereof to a zone of lower concentration thereof to further form the dielectric barrier. Various apparatus are made by the process.

Abstract translation: 在后端金属化的层间电介质层（ILD）中形成绝缘线的工艺包括在使阻挡前体中的至少一个合金元素引起的金属屏障前体之间形成电介质势垒 ILD。 因此，介电阻挡层是自形成的自对准势垒。 热处理在使至少一种合金元素从其较高浓度的区域迁移到其较低浓度的区域的条件下进行以进一步形成电介质阻挡层。 通过该方法制造各种装置。

公开(公告)号：US20150084198A1

公开(公告)日：2015-03-26

申请号：US14038502

申请日：2013-09-26

Applicant: HUI JAE YOO ,  TEJASWI K. INDUKURI ,  RAMANAN V. CHEBIAM ,  JAMES S. CLARKE

Inventor： HUI JAE YOO ,  TEJASWI K. INDUKURI ,  RAMANAN V. CHEBIAM ,  JAMES S. CLARKE

IPC: H01L23/00

CPC classification number: H01L21/76849 ,  H01L21/76838 ,  H01L21/76843 ,  H01L21/76877 ,  H01L21/76882 ,  H01L23/53209 ,  H01L23/53214 ,  H01L23/53228 ,  H01L23/53238 ,  H01L23/53242 ,  H01L23/53252 ,  H01L23/53257 ,  H01L23/53266 ,  H01L2224/45015 ,  H01L2924/0002 ,  H01L2924/00011 ,  H01L2924/00

Abstract: A dielectric layer and a method of forming thereof. An opening defined in a dielectric layer and a wire deposited within the opening, wherein the wire includes a core material surrounded by a jacket material, wherein the jacket material exhibits a first resistivity ρ1 and the core material exhibits a second resistivity ρ2 and ρ2 is less than ρ1.

Abstract translation: 介电层及其形成方法。 限定在介电层中的开口和沉积在开口内的电线，其中所述电线包括由护套材料围绕的芯材料，其中所述护套材料表现出第一电阻率1，并且所述芯材料表现出第二电阻率 和＆rgr; 2小于＆rgr; 1。

公开(公告)号：US20150001724A1

公开(公告)日：2015-01-01

申请号：US13931219

申请日：2013-06-28

Applicant: Manish CHANDHOK ,  Hui Jae Yoo ,  Yan A. Borodovsky ,  Florian Gstrein ,  David N. Shykind ,  Kevin L. Lin

Inventor： Manish CHANDHOK ,  Hui Jae Yoo ,  Yan A. Borodovsky ,  Florian Gstrein ,  David N. Shykind ,  Kevin L. Lin

IPC: H01L23/535 ,  H01L21/768

CPC classification number: H01L23/5226 ,  H01L21/32133 ,  H01L21/32139 ,  H01L21/76802 ,  H01L21/7682 ,  H01L21/76877 ,  H01L21/76879 ,  H01L21/76883 ,  H01L21/76885 ,  H01L21/76886 ,  H01L21/76897 ,  H01L23/5222 ,  H01L23/528 ,  H01L23/53209 ,  H01L23/53271 ,  H01L23/5329 ,  H01L23/53295 ,  H01L23/535 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method including patterning a thickness dimension of an interconnect material into a thickness dimension for a wiring line with one or more vias extending from the wiring line and introducing a dielectric material on the interconnect material. A method including depositing and patterning an interconnect material into a wiring line and one or more vias; and introducing a dielectric material on the interconnect material such that the one or more vias are exposed through the dielectric material. An apparatus including a first interconnect layer in a first plane and a second interconnect in a second plane on a substrate; and a dielectric layer separating the first and second interconnect layers, wherein the first interconnect layer comprises a monolith including a wiring line and at least one via, the at least one via extending from the wiring line to a wiring line of the second interconnect layer.

Abstract translation: 一种方法，包括将互连材料的厚度尺寸图案化为具有从布线延伸的一个或多个通孔的布线的厚度尺寸，并将介电材料引入到互连材料上。 一种包括将互连材料沉积和图案化成布线和一个或多个通孔的方法; 以及在所述互连材料上引入介电材料，使得所述一个或多个通孔通过所述介电材料暴露。 一种装置，包括在第一平面中的第一互连层和在衬底上的第二平面中的第二互连; 以及分离所述第一和第二互连层的电介质层，其中所述第一互连层包括包括布线和至少一个通孔的整体，所述至少一个通孔从所述布线延伸到所述第二互连层的布线。

公开(公告)号：US20090001594A1

公开(公告)日：2009-01-01

申请号：US11771091

申请日：2007-06-29

Applicant: Hui Jae Yoo ,  Makarem A. Hussein ,  Jeffery D. Bielefeld ,  Vijayakumar S. Ramachandrarao

Inventor： Hui Jae Yoo ,  Makarem A. Hussein ,  Jeffery D. Bielefeld ,  Vijayakumar S. Ramachandrarao

IPC: H01L23/52 ,  H01L21/4763

CPC classification number: H01L23/53295 ,  H01L21/7682 ,  H01L23/5222 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method may comprise assembling a first dielectric ensemble that comprises a first dielectric layer exhibiting a first porosity, a second dielectric layer exhibiting a second porosity and a third dielectric layer exhibiting a third porosity, and fabricating a first metal line in the dielectric ensemble. A chemical may be applied on the third layer to pass through and dissolve a portion of the second layer. The third layer acts to prevent a via that is partially landed on the dielectric from exposing the air gap underneath.

Abstract translation: 一种方法可以包括组装第一介电体集合，其包括表现出第一孔隙率的第一电介质层，表现出第二孔隙率的第二电介质层和表现出第三孔隙率的第三电介质层，以及在电介质集合体中制造第一金属线。 化学品可以施加在第三层上以通过并溶解第二层的一部分。 第三层用于防止部分落在电介质上的通孔露出下方的气隙。