公开(公告)号：US08642433B2

公开(公告)日：2014-02-04

申请号：US13509551

申请日：2011-12-05

申请人： Huicai Zhong ,  Jun Luo ,  Chao Zhao ,  Qingqing Liang

发明人： Huicai Zhong ,  Jun Luo ,  Chao Zhao ,  Qingqing Liang

IPC分类号： H01L21/336 ,  H01L21/477

CPC分类号： H01L29/6653 ,  H01L29/78

摘要： A method for manufacturing a semiconductor device is disclosed, comprising: providing a substrate, a gate region on the substrate and a semiconductor region at both sides of the gate region; forming sacrificial spacers, which cover a portion of the semiconductor region, on sidewalls of the gate region; forming a metal layer on a portion of the semiconductor region outside the sacrificial spacers and on the gate region; removing the sacrificial spacers; performing annealing so that the metal layer reacts with the semiconductor region to form a metal-semiconductor compound layer on the semiconductor region; and removing unreacted metal layer. By separating the metal layer from the channel and the gate region of the device with the thickness of the sacrificial spacers, the effect of metal layer diffusion on the channel and the gate region is reduced and performance of the device is improved.

摘要翻译： 公开了一种制造半导体器件的方法，包括：提供衬底，衬底上的栅极区域和栅极区两侧的半导体区域; 在所述栅极区域的侧壁上形成覆盖所述半导体区域的一部分的牺牲间隔物; 在牺牲间隔物外部和栅极区域上的半导体区域的一部分上形成金属层; 去除牺牲隔离物; 进行退火，使得金属层与半导体区域反应，以在半导体区域上形成金属 - 半导体化合物层; 并除去未反应的金属层。 通过将金属层与器件的栅极区域与牺牲间隔物的厚度分开，金属层扩散对沟道和栅极区域的影响降低，并且器件的性能得到改善。

公开(公告)号：US20130045588A1

公开(公告)日：2013-02-21

申请号：US13509551

申请日：2011-12-05

申请人： Huicai Zhong ,  Jun Luo ,  Chao Zhao ,  Qingqing Liang

发明人： Huicai Zhong ,  Jun Luo ,  Chao Zhao ,  Qingqing Liang

IPC分类号： H01L21/20

CPC分类号： H01L29/6653 ,  H01L29/78

摘要： A method for manufacturing a semiconductor device is disclosed, comprising: providing a substrate, a gate region on the substrate and a semiconductor region at both sides of the gate region; forming sacrificial spacers, which cover a portion of the semiconductor region, on sidewalls of the gate region; forming a metal layer on a portion of the semiconductor region outside the sacrificial spacers and on the gate region; removing the sacrificial spacers; performing annealing so that the metal layer reacts with the semiconductor region to form a metal-semiconductor compound layer on the semiconductor region; and removing unreacted metal layer. By separating the metal layer from the channel and the gate region of the device with the thickness of the sacrificial spacers, the effect of metal layer diffusion on the channel and the gate region is reduced and performance of the device is improved.

摘要翻译： 公开了一种制造半导体器件的方法，包括：提供衬底，衬底上的栅极区域和栅极区两侧的半导体区域; 在所述栅极区域的侧壁上形成覆盖所述半导体区域的一部分的牺牲间隔物; 在牺牲间隔物外部和栅极区域上的半导体区域的一部分上形成金属层; 去除牺牲隔离物; 进行退火，使得金属层与半导体区域反应，以在半导体区域上形成金属 - 半导体化合物层; 并除去未反应的金属层。 通过将金属层与器件的栅极区域与牺牲间隔物的厚度分开，金属层扩散对沟道和栅极区域的影响降低，并且器件的性能得到改善。

公开(公告)号：US09070719B2

公开(公告)日：2015-06-30

申请号：US13577942

申请日：2011-11-18

申请人： Huicai Zhong ,  Qingqing Liang ,  Jun Luo ,  Chao Zhao

发明人： Huicai Zhong ,  Qingqing Liang ,  Jun Luo ,  Chao Zhao

IPC分类号： H01L21/762 ,  H01L21/336 ,  H01L29/78 ,  H01L29/66 ,  H01L21/8234 ,  H01L21/8238 ,  H01L29/06 ,  H01L21/84

CPC分类号： H01L29/66795 ,  H01L21/823431 ,  H01L21/823481 ,  H01L21/823821 ,  H01L21/823878 ,  H01L21/845 ,  H01L29/0649 ,  H01L29/66545 ,  H01L29/785

摘要： A semiconductor device structure, a method for manufacturing the same, and a method for manufacturing a semiconductor fin are disclosed. In one embodiment, the method for manufacturing the semiconductor device structure comprises: forming a fin in a first direction on a semiconductor substrate; forming a gate line in a second direction, the second direction crossing the first direction on the semiconductor substrate, and the gate line intersecting the fin with a gate dielectric layer sandwiched between the gate line and the fin; forming a dielectric spacer surrounding the gate line; and performing inter-device electrical isolation at a predetermined position, wherein isolated portions of the gate line form independent gate electrodes of respective devices.

摘要翻译： 公开了一种半导体器件结构，其制造方法和半导体鳍片的制造方法。 在一个实施例中，制造半导体器件结构的方法包括：在半导体衬底上沿第一方向形成翅片; 在第二方向上形成栅极线，在半导体衬底上与第一方向交叉的第二方向和与鳍状物交叉的栅极线与夹在栅极线和鳍之间的栅极电介质层形成栅极线; 形成围绕所述栅极线的介电隔离层; 以及在预定位置执行器件间电隔离，其中所述栅极线的隔离部分形成各个器件的独立栅电极。

公开(公告)号：US20130062708A1

公开(公告)日：2013-03-14

申请号：US13577942

申请日：2011-11-18

申请人： Huicai Zhong ,  Qingqing Liang ,  Jun Luo ,  Chao Zhao

发明人： Huicai Zhong ,  Qingqing Liang ,  Jun Luo ,  Chao Zhao

IPC分类号： H01L21/762 ,  H01L27/088

CPC分类号： H01L29/66795 ,  H01L21/823431 ,  H01L21/823481 ,  H01L21/823821 ,  H01L21/823878 ,  H01L21/845 ,  H01L29/0649 ,  H01L29/66545 ,  H01L29/785

摘要： A semiconductor device structure, a method for manufacturing the same, and a method for manufacturing a semiconductor fin are disclosed. In one embodiment, the method for manufacturing the semiconductor device structure comprises: forming a fin in a first direction on a semiconductor substrate; forming a gate line in a second direction, the second direction crossing the first direction on the semiconductor substrate, and the gate line intersecting the fin with a gate dielectric layer sandwiched between the gate line and the fin; forming a dielectric spacer surrounding the gate line; and performing inter-device electrical isolation at a predetermined position, wherein isolated portions of the gate line form independent gate electrodes of respective devices.

摘要翻译： 公开了一种半导体器件结构，其制造方法和半导体鳍片的制造方法。 在一个实施例中，制造半导体器件结构的方法包括：在半导体衬底上沿第一方向形成翅片; 在第二方向上形成栅极线，在半导体衬底上与第一方向交叉的第二方向和与鳍状物交叉的栅极线与夹在栅极线和鳍之间的栅极电介质层形成栅极线; 形成围绕所述栅极线的介电隔离层; 以及在预定位置执行器件间电隔离，其中所述栅极线的隔离部分形成各个器件的独立栅电极。

公开(公告)号：US09419108B2

公开(公告)日：2016-08-16

申请号：US14406904

申请日：2012-08-17

申请人： Qingqing Liang ,  Huicai Zhong ,  Huilong Zhu ,  Chao Zhao ,  Tianchun Ye

发明人： Qingqing Liang ,  Huicai Zhong ,  Huilong Zhu ,  Chao Zhao ,  Tianchun Ye

IPC分类号： H01L29/66 ,  H01L29/78

CPC分类号： H01L29/66795 ,  H01L29/785 ,  H01L29/7855

摘要： One embodiment of present invention provides a method for manufacturing a semiconductor structure, which comprises: forming a gate stack on a semiconductor substrate and removing parts of the substrates situated on two sides of the gate stack; forming sidewall spacers on sidewalls of the gate stack and on sidewalls of the part of the substrate under the gate stack; forming doped regions in parts of the substrate on two sides of the gate stack, and forming a first dielectric layer to cover the entire semiconductor structure; selectively removing parts of the gate stack and parts of the first dielectric layer to form a channel region opening and source/drain region openings; forming a high K dielectric layer on sidewalls of the channel region opening; and implementing epitaxy process to form a continuous fin structure that spans across the channel region opening and the source/drain region openings.

摘要翻译： 本发明的一个实施例提供了一种用于制造半导体结构的方法，其包括：在半导体衬底上形成栅极叠层并去除位于栅极叠层两侧的衬底的部分; 在所述栅极堆叠的侧壁上以及在所述栅极堆叠下的所述衬底的所述部分的侧壁上形成侧壁间隔物; 在所述栅极堆叠的两侧上在所述衬底的部分中形成掺杂区域，以及形成覆盖整个半导体结构的第一介电层; 选择性地去除所述栅极堆叠的部分和所述第一介电层的部分以形成沟道区域开口和源极/漏极区域开口; 在沟道区域开口的侧壁上形成高K电介质层; 并且实现外延工艺以形成跨越沟道区域开口和源极/漏极区域开口的连续翅片结构。

公开(公告)号：US20150236134A1

公开(公告)日：2015-08-20

申请号：US14412237

申请日：2012-07-18

申请人： Huicai Zhong ,  Qingqing Liang ,  Chao Zhao

发明人： Huicai Zhong ,  Qingqing Liang ,  Chao Zhao

IPC分类号： H01L29/66

CPC分类号： H01L29/66795 ,  H01L21/268 ,  H01L21/76283 ,  H01L29/665 ,  H01L29/785

摘要： A method of manufacturing a FinFET semiconductor device is provided, wherein the semiconductor fins are formed in a parallel arrangement which intersects the gates arranged in parallel. The polycrystalline silicon layer is deposited and then converted into a single crystal silicon layer such that the single crystal silicon layer and the semiconductor fins are integrated in essence, i.e., the source/drain region in the semiconductor fins is raised and the top area of the semiconductor fins is extended. Subsequently, the single crystal silicon layer above the top of the semiconductor fins is converted into a metal silicide so as to form a source/drain region contact. The source/drain region contact in the present invention has a larger area than that in a conventional FinFET, which decreases the contact resistance and facilitates the formation of a self-aligned metal plug in the follow-up process.

摘要翻译： 提供一种制造FinFET半导体器件的方法，其中半导体鳍片形成为与并行布置的栅极相交的平行布置。 沉积多晶硅层，然后转换为单晶硅层，使得单晶硅层和半导体鳍片本质上是集成的，即半导体鳍片中的源极/漏极区域被升高，并且顶部区域 半导体鳍片延伸。 随后，将半导体鳍片顶部上方的单晶硅层转换为金属硅化物，以形成源极/漏极区域接触。 本发明中的源极/漏极区域的接触面积大于传统的FinFET的面积，这在以后的过程中降低了接触电阻并且有利于形成自对准的金属插塞。

公开(公告)号：US08748983B2

公开(公告)日：2014-06-10

申请号：US13380828

申请日：2011-08-12

申请人： Huicai Zhong ,  Chao Zhao ,  Qingqing Liang

发明人： Huicai Zhong ,  Chao Zhao ,  Qingqing Liang

IPC分类号： H01L27/12 ,  H01L21/70

CPC分类号： H01L29/0847 ,  H01L29/165 ,  H01L29/66636 ,  H01L29/78 ,  H01L29/7848

摘要： An embedded source/drain MOS transistor and a formation method thereof are provided. The embedded source/drain MOS transistor comprises: a semiconductor substrate; a gate structure on the semiconductor substrate; and a source/drain stack embedded in the semiconductor substrate at both sides of the gate structure with an upper surface of the source/drain stack being exposed, wherein the source/drain stack comprises a dielectric layer and a semiconductor layer above the dielectric layer. The present invention can cut off the path for the leakage current from the source region and the drain region to the semiconductor substrate, thereby reducing the leakage current from the source region and the drain region to the semiconductor substrate.

摘要翻译： 提供一种嵌入式源极/漏极MOS晶体管及其形成方法。 嵌入式源极/漏极MOS晶体管包括：半导体衬底; 半导体衬底上的栅极结构; 以及在源极/漏极叠层的上表面被暴露的栅极结构的两侧嵌入在半导体衬底中的源极/漏极堆叠，其中源极/漏极叠层包括电介质层和介电层上方的半导体层。 本发明可以切断从源极区域和漏极区域到半导体衬底的漏电流的路径，从而减少从源极区域和漏极区域到半导体衬底的漏电流。

公开(公告)号：US20130228893A1

公开(公告)日：2013-09-05

申请号：US13145301

申请日：2011-04-22

申请人： Huicai Zhong ,  Chao Zhao ,  Qingqing Liang

发明人： Huicai Zhong ,  Chao Zhao ,  Qingqing Liang

IPC分类号： H01L21/762 ,  H01L29/02

CPC分类号： H01L21/76224 ,  H01L21/76232 ,  H01L29/02

摘要： A trench isolation structure and a method of forming the same are provided. The trench isolation structure includes: a semiconductor substrate, and trenches formed on the surface of the semiconductor substrate and filled with a dielectric layer, wherein the material of the dielectric layer is a crystalline material. By using the present invention, the size of the divot can be reduced, and device performances can be improved.

摘要翻译： 提供了沟槽隔离结构及其形成方法。 沟槽隔离结构包括：半导体衬底和形成在半导体衬底的表面上并填充有电介质层的沟槽，其中电介质层的材料是结晶材料。 通过使用本发明，可以减小纹路的尺寸，并且可以提高器件性能。

公开(公告)号：US20130037859A1

公开(公告)日：2013-02-14

申请号：US13321852

申请日：2011-08-12

申请人： Huicai Zhong ,  Qingqing Liang ,  Chao Zhao ,  Huilong Zhu

发明人： Huicai Zhong ,  Qingqing Liang ,  Chao Zhao ,  Huilong Zhu

IPC分类号： H01L27/10 ,  H01L21/326 ,  H01L23/522 ,  H01L29/788 ,  H01L29/92 ,  H01L23/525

CPC分类号： H01L23/481 ,  H01L23/525 ,  H01L23/5252 ,  H01L23/5256 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device and a method for programming the same are provided. The semiconductor device comprises: a semiconductor substrate with an interconnect formed therein; a Through-Silicon Via (TSV) penetrating through the semiconductor substrate; and a programmable device which can be switched between on and off states, the TSV being connected to the interconnect by the programmable device. The present invention is beneficial in improving flexibility of TSV application.

摘要翻译： 提供了半导体器件及其编程方法。 半导体器件包括：其中形成有互连的半导体衬底; 穿透半导体衬底的透硅通孔（TSV）; 以及可以在导通和关断状态之间切换的可编程器件，TSV通过可编程器件连接到互连。 本发明有利于提高TSV应用的灵活性。

公开(公告)号：US20120273886A1

公开(公告)日：2012-11-01

申请号：US13380828

申请日：2011-08-12

申请人： Huicai Zhong ,  Chao Zhao ,  Qingqing Liang

发明人： Huicai Zhong ,  Chao Zhao ,  Qingqing Liang

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/0847 ,  H01L29/165 ,  H01L29/66636 ,  H01L29/78 ,  H01L29/7848

摘要： An embedded source/drain MOS transistor and a formation method thereof are provided. The embedded source/drain MOS transistor comprises: a semiconductor substrate; a gate structure on the semiconductor substrate; and a source/drain stack embedded in the semiconductor substrate at both sides of the gate structure with an upper surface of the source/drain stack being exposed, wherein the source/drain stack comprises a dielectric layer and a semiconductor layer above the dielectric layer. The present invention can cut off the path for the leakage current from the source region and the drain region to the semiconductor substrate, thereby reducing the leakage current from the source region and the drain region to the semiconductor substrate.

摘要翻译： 提供一种嵌入式源极/漏极MOS晶体管及其形成方法。 嵌入式源极/漏极MOS晶体管包括：半导体衬底; 半导体衬底上的栅极结构; 以及在源极/漏极叠层的上表面被暴露的栅极结构的两侧嵌入在半导体衬底中的源极/漏极堆叠，其中源极/漏极叠层包括电介质层和介电层上方的半导体层。 本发明可以切断从源极区域和漏极区域到半导体衬底的漏电流的路径，从而减少从源极区域和漏极区域到半导体衬底的漏电流。