公开(公告)号：US20070045611A1

公开(公告)日：2007-03-01

申请号：US11162126

申请日：2005-08-30

申请人： Huilong Zhu ,  Xiangdong Chen

发明人： Huilong Zhu ,  Xiangdong Chen

IPC分类号： H01L29/06

CPC分类号： H01L21/26506 ,  H01L21/28132 ,  H01L29/1054 ,  H01L29/6656 ,  H01L29/66636 ,  H01L29/66659 ,  H01L29/66742 ,  H01L29/7834 ,  H01L29/78684 ,  H01L29/78696

摘要： The present invention relates generally to a semiconductor device having a channel region comprising a semiconductor alloy of a first semiconductor material and a second, different material, and wherein atomic distribution of the second material in the channel region is graded along a direction that is substantially parallel to a substrate surface in which the semiconductor device is located. Specifically, the semiconductor device comprises a field effect transistor (FET) that has a SiGe channel with a laterally graded germanium content.

摘要翻译： 本发明一般涉及具有包括第一半导体材料和第二不同材料的半导体合金的沟道区的半导体器件，并且其中沟道区中的第二材料的原子分布沿着基本平行的方向分级 到半导体器件所在的衬底表面。 具体地，半导体器件包括具有横向渐变的锗含量的SiGe沟道的场效应晶体管（FET）。

公开(公告)号：US07442585B2

公开(公告)日：2008-10-28

申请号：US11162126

申请日：2005-08-30

申请人： Huilong Zhu ,  Xiangdong Chen

发明人： Huilong Zhu ,  Xiangdong Chen

IPC分类号： H01L21/00

CPC分类号： H01L21/26506 ,  H01L21/28132 ,  H01L29/1054 ,  H01L29/6656 ,  H01L29/66636 ,  H01L29/66659 ,  H01L29/66742 ,  H01L29/7834 ,  H01L29/78684 ,  H01L29/78696

摘要： The present invention relates generally to a semiconductor device having a channel region comprising a semiconductor alloy of a first semiconductor material and a second, different material, and wherein atomic distribution of the second material in the channel region is graded along a direction that is substantially parallel to a substrate surface in which the semiconductor device is located. Specifically, the semiconductor device comprises a field effect transistor (FET) that has a SiGe channel with a laterally graded germanium content.

摘要翻译： 本发明一般涉及具有包括第一半导体材料和第二不同材料的半导体合金的沟道区的半导体器件，并且其中沟道区中的第二材料的原子分布沿着基本平行的方向分级 到半导体器件所在的衬底表面。 具体地，半导体器件包括具有横向渐变的锗含量的SiGe沟道的场效应晶体管（FET）。

公开(公告)号：US20080237733A1

公开(公告)日：2008-10-02

申请号：US11691699

申请日：2007-03-27

申请人： Xiangdong Chen ,  Zhijiong Luo ,  Huilong Zhu

发明人： Xiangdong Chen ,  Zhijiong Luo ,  Huilong Zhu

IPC分类号： H01L29/78 ,  H01L21/8232

CPC分类号： H01L21/823878 ,  H01L21/823807 ,  H01L29/665 ,  H01L29/7843 ,  H01L29/7846

摘要： The embodiments of the invention provide a structure and method to enhance channel stress by using optimized STI stress and nitride capping layer stress. More specifically, a transistor structure is provided comprising a substrate having a first transistor region and a second transistor region, different than the first transistor region. Moreover, first transistors are provided over the first transistor region and second transistors, different than the first transistors, are provided over the second transistors region. The first transistor comprises an NFET and the second transistor comprises a PFET. The structure further includes STI regions in the substrate adjacent sides of the first transistors and the second transistors, wherein the STI regions comprise stress producing regions. Recesses are within at least two of the STI regions, such that portions of at least one of said first stress liner and said second stress liner are positioned within said recesses.

摘要翻译： 本发明的实施例提供了通过使用优化的STI应力和氮化物覆盖层应力来增强通道应力的结构和方法。 更具体地，提供了晶体管结构，其包括具有不同于第一晶体管区域的第一晶体管区域和第二晶体管区域的衬底。 此外，在第一晶体管区域上提供第一晶体管，并且在第二晶体管区域上提供与第一晶体管不同的第二晶体管。 第一晶体管包括NFET，第二晶体管包括PFET。 该结构还包括在第一晶体管和第二晶体管的相邻侧面的衬底中的STI区域，其中STI区域包括应力产生区域。 凹陷部位在至少两个STI区域内，使得至少一个所述第一应力衬垫和所述第二应力衬垫的部分位于所述凹部内。

公开(公告)号：US07309901B2

公开(公告)日：2007-12-18

申请号：US10908087

申请日：2005-04-27

申请人： Xiangdong Chen ,  Sunfei Fang ,  Zhijiong Luo ,  Haining Yang ,  Huilong Zhu

发明人： Xiangdong Chen ,  Sunfei Fang ,  Zhijiong Luo ,  Haining Yang ,  Huilong Zhu

IPC分类号： H01L21/8232

CPC分类号： H01L29/7833 ,  H01L29/665 ,  H01L29/6659

摘要： A semiconductor structure and method for forming the same. The semiconductor structure comprises a field effect transistor (FET) having a channel region disposed between first and second source/drain (S/D) extension regions which are in turn in direct physical contact with first and second S/D regions, respective. First and second silicide regions are formed such that the first silicide region is in direct physical contact with the first S/D region and the first S/D extension region, whereas the second silicide region is in direct physical contact with the second S/D region and the second S/D extension region. The first silicide region is thinner for regions in contact with first S/D extension region than for regions in contact with the first S/D region. Similarly, the second silicide region is thinner for regions in contact with second S/D extension region than for regions in contact with the second S/D region.

摘要翻译： 一种半导体结构及其形成方法。 半导体结构包括场效应晶体管（FET），其具有设置在第一和第二源极/漏极（S / D）延伸区域之间的沟道区域，第一和第二源极/漏极（S / D）延伸区域又分别与第一和第二S / D区域直接物理接触。 形成第一和第二硅化物区域，使得第一硅化物区域与第一S / D区域和第一S / D延伸区域直接物理接触，而第二硅化物区域与第二S / D区域直接物理接触 区域和第二S / D扩展区域。 对于与第一S / D延伸区域接触的区域，第一硅化物区域比与第一S / D区域接触的区域更薄。 类似地，对于与第二S / D延伸区域接触的区域，第二硅化物区域比与第二S / D区域接触的区域更薄。

公开(公告)号：US20090014794A1

公开(公告)日：2009-01-15

申请号：US12238041

申请日：2008-09-25

申请人： Huilong Zhu ,  Xiangdong Chen

发明人： Huilong Zhu ,  Xiangdong Chen

IPC分类号： H01L47/00

CPC分类号： H01L21/26506 ,  H01L21/28132 ,  H01L29/1054 ,  H01L29/6656 ,  H01L29/66636 ,  H01L29/66659 ,  H01L29/66742 ,  H01L29/7834 ,  H01L29/78684 ,  H01L29/78696

摘要： The present invention relates generally to a semiconductor device having a channel region comprising a semiconductor alloy of a first semiconductor material and a second, different material, and wherein atomic distribution of the second material in the channel region is graded along a direction that is substantially parallel to a substrate surface in which the semiconductor device is located. Specifically, the semiconductor device comprises a field effect transistor (FET) that has a SiGe channel with a laterally graded germanium content.

摘要翻译： 本发明一般涉及具有包括第一半导体材料和第二不同材料的半导体合金的沟道区的半导体器件，并且其中沟道区中的第二材料的原子分布沿着基本平行的方向分级 到半导体器件所在的衬底表面。 具体地，半导体器件包括具有横向渐变的锗含量的SiGe沟道的场效应晶体管（FET）。

公开(公告)号：US06972461B1

公开(公告)日：2005-12-06

申请号：US10710274

申请日：2004-06-30

申请人： Xiangdong Chen ,  Dureseti Chidambarrao ,  Geng Wang ,  Huilong Zhu

发明人： Xiangdong Chen ,  Dureseti Chidambarrao ,  Geng Wang ,  Huilong Zhu

IPC分类号： H01L21/336 ,  H01L21/8244 ,  H01L27/01 ,  H01L27/11 ,  H01L29/786

CPC分类号： H01L29/785 ,  H01L27/11 ,  H01L27/1108 ,  H01L29/66795 ,  H01L29/78687 ,  Y10S438/933

摘要： A structure for use as a MOSFET employs an SOI wafer with a SiGe island resting on the SOI layer and extending between two blocks that serve as source and drain; epitaxially grown Si on the vertical surfaces of the SiGe forms the transistor channel. The lattice structure of the SiGe is arranged such that the epitaxial Si has little or no strain in the direction between the S and D and a significant strain perpendicular to that direction.

摘要翻译： 用作MOSFET的结构采用具有SiGe岛的SOI晶片，其位于SOI层上并在用作源极和漏极的两个块之间延伸; 在SiGe的垂直表面上外延生长的Si形成晶体管沟道。 SiGe的晶格结构被布置成使得外延Si在S和D之间的方向上几乎没有或没有应变，并且垂直于该方向的显着应变。

公开(公告)号：US07816219B2

公开(公告)日：2010-10-19

申请号：US11850076

申请日：2007-09-05

申请人： Xiangdong Chen ,  Sunfei Fang ,  Zhijiong Luo ,  Haining Yang ,  Huilong Zhu

发明人： Xiangdong Chen ,  Sunfei Fang ,  Zhijiong Luo ,  Haining Yang ,  Huilong Zhu

IPC分类号： H01L21/336

CPC分类号： H01L29/7833 ,  H01L29/665 ,  H01L29/6659

摘要： A semiconductor structure and method for forming the same. First, a semiconductor structure is provided, including (a) a semiconductor layer including (i) a channel region and (ii) first and second source/drain (S/D) extension regions, and (iii) first and second S/D regions, (b) a gate dielectric region in direction physical contact with the channel region via a first interfacing surface that defines a reference direction essentially perpendicular to the first interfacing surface, and (c) a gate region in direct physical contact with the gate dielectric region, wherein the gate dielectric region is sandwiched between and electrically insulates the gate region and the channel region. Then, (i) a first shallow contact region is formed in direct physical contact with the first S/D extension region, and (ii) a first deep contact region is formed in direct physical contact with the first S/D region and the first shallow contact region.

摘要翻译： 一种半导体结构及其形成方法。 首先，提供半导体结构，其包括（a）包括（i）沟道区和（ii）第一和第二源/漏（S / D）延伸区的半导体层，以及（iii）第一和第二S / D 区域，（b）通过限定基本上垂直于第一接口表面的参考方向的第一接口表面方向与沟道区域物理接触的栅极电介质区域，以及（c）与栅极电介质直接物理接触的栅极区域 区域，其中栅极电介质区域夹在栅极区域和沟道区域之间并使电绝缘。 然后，（i）第一浅接触区域形成为与第一S / D延伸区域直接物理接触，并且（ii）第一深接触区域形成为与第一S / D区域和第一浅/ 浅接触区域。

公开(公告)号：US20070298572A1

公开(公告)日：2007-12-27

申请号：US11850076

申请日：2007-09-05

申请人： Xiangdong Chen ,  Sunfei Fang ,  Zhijiong Luo ,  Haining Yang ,  Huilong Zhu

发明人： Xiangdong Chen ,  Sunfei Fang ,  Zhijiong Luo ,  Haining Yang ,  Huilong Zhu

IPC分类号： H01L21/336

CPC分类号： H01L29/7833 ,  H01L29/665 ,  H01L29/6659

摘要： A semiconductor structure and method for forming the same. First, a semiconductor structure is provided, including (a) a semiconductor layer including (i) a channel region and (ii) first and second source/drain (S/D) extension regions, and (iii) first and second S/D regions, (b) a gate dielectric region in direction physical contact with the channel region via a first interfacing surface that defines a reference direction essentially perpendicular to the first interfacing surface, and (c) a gate region in direct physical contact with the gate dielectric region, wherein the gate dielectric region is sandwiched between and electrically insulates the gate region and the channel region. Then, (i) a first shallow contact region is formed in direct physical contact with the first S/D extension region, and (ii) a first deep contact region is formed in direct physical contact with the first S/D region and the first shallow contact region.

摘要翻译： 一种半导体结构及其形成方法。 首先，提供半导体结构，其包括（a）包括（i）沟道区和（ii）第一和第二源/漏（S / D）延伸区的半导体层，以及（iii）第一和第二S / D 区域，（b）通过限定基本上垂直于第一接口表面的参考方向的第一接口表面方向与沟道区域物理接触的栅极电介质区域，以及（c）与栅极电介质直接物理接触的栅极区域 区域，其中栅极电介质区域夹在栅极区域和沟道区域之间并使电绝缘。 然后，（i）第一浅接触区域形成为与第一S / D延伸区域直接物理接触，并且（ii）第一深接触区域形成为与第一S / D区域和第一浅/ 浅接触区域。

公开(公告)号：US20060244075A1

公开(公告)日：2006-11-02

申请号：US10908087

申请日：2005-04-27

申请人： Xiangdong Chen ,  Sunfei Fang ,  Zhijiong Luo ,  Haining Yang ,  Huilong Zhu

发明人： Xiangdong Chen ,  Sunfei Fang ,  Zhijiong Luo ,  Haining Yang ,  Huilong Zhu

IPC分类号： H01L29/76

CPC分类号： H01L29/7833 ,  H01L29/665 ,  H01L29/6659

摘要： A semiconductor structure and method for forming the same. The semiconductor structure comprises a field effect transistor (FET) having a channel region disposed between first and second source/drain (S/D) extension regions which are in turn in direct physical contact with first and second S/D regions, respective. First and second silicide regions are formed such that the first silicide region is in direct physical contact with the first S/D region and the first S/D extension region, whereas the second silicide region is in direct physical contact with the second S/D region and the second S/D extension region. The first silicide region is thinner for regions in contact with first S/D extension region than for regions in contact with the first S/D region. Similarly, the second silicide region is thinner for regions in contact with second S/D extension region than for regions in contact with the second S/D region.

摘要翻译： 一种半导体结构及其形成方法。 半导体结构包括场效应晶体管（FET），其具有设置在第一和第二源极/漏极（S / D）延伸区域之间的沟道区域，第一和第二源极/漏极（S / D）延伸区域又分别与第一和第二S / D区域直接物理接触。 形成第一和第二硅化物区域，使得第一硅化物区域与第一S / D区域和第一S / D延伸区域直接物理接触，而第二硅化物区域与第二S / D区域直接物理接触 区域和第二S / D扩展区域。 对于与第一S / D延伸区域接触的区域，第一硅化物区域比与第一S / D区域接触的区域更薄。 类似地，对于与第二S / D延伸区域接触的区域，第二硅化物区域比与第二S / D区域接触的区域更薄。

公开(公告)号：US09082751B2

公开(公告)日：2015-07-14

申请号：US13232737

申请日：2011-09-14

申请人： Xiangdong Chen ,  Wei Xia

发明人： Xiangdong Chen ,  Wei Xia

IPC分类号： H01L29/66 ,  H01L29/423 ,  H01L29/78 ,  H01L29/06

CPC分类号： H01L29/4236 ,  H01L29/0653 ,  H01L29/0692 ,  H01L29/66659 ,  H01L29/66787 ,  H01L29/7835 ,  H01L29/785

摘要： According to one embodiment, a half-FinFET semiconductor device comprises a gate structure formed over a semiconductor body. The semiconductor body includes a source region comprised of a plurality of fins extending beyond a first side of the gate structure and a continuous drain region adjacent a second side of the gate structure opposite the plurality of fins. The continuous drain region causes the half-FinFET semiconductor device to have a reduced ON-resistance. A method for fabricating a semiconductor device having a half-FinFET structure comprises designating source and drain regions in a semiconductor body, etching the source region to produce a plurality of source fins while masking the drain region during the etching to provide a continuous drain region, thereby resulting in the half-FinFET structure having a reduced ON-resistance.

摘要翻译： 根据一个实施例，半FinFET半导体器件包括形成在半导体本体上的栅极结构。 半导体本体包括源极区域，该区域包括延伸超过栅极结构的第一侧面的多个鳍片，以及与栅极结构的与多个鳍片相对的第二侧相邻的连续漏极区域。 连续漏极区域使得半FinFET半导体器件具有降低的导通电阻。 一种制造具有半FinFET结构的半导体器件的方法包括：在半导体本体中指定源极和漏极区域，蚀刻源极区域以产生多个源极鳍片，同时在蚀刻期间掩蔽漏极区域以提供连续的漏极区域， 从而导致半FinFET结构具有降低的导通电阻。