公开(公告)号：US20070296007A1

公开(公告)日：2007-12-27

申请号：US11369195

申请日：2006-03-06

申请人： Human Park ,  Ulrich Klostermann

发明人： Human Park ,  Ulrich Klostermann

IPC分类号： H01L29/772 ,  G11C11/00

CPC分类号： G11C11/16 ,  B82Y10/00 ,  H01L27/228

摘要： A buried ground contact that connects the ground electrodes of transistors in adjacent memory cells that are separated by an isolation region is described. In some embodiments, the buried ground contact passes beneath the isolation region that separates cells to electrically connect the drain regions of transistors in adjacent cells. The buried ground may be connected to a metal ground line through via connections at intervals, outside of the active cell area. Use of this buried ground contact eliminates the need for individual ground connections to each cell, leading to a substantial reduction in cell size, and a consequent increase in cell density. The buried ground contacts of the invention can be used with a variety of devices, including MRAM and PCRAM devices.

摘要翻译： 描述了连接由隔离区分隔开的相邻存储单元中的晶体管的接地电极的埋地接地触点。 在一些实施例中，埋地接触通过隔离单元的隔离区下方，以电连接相邻单元中的晶体管的漏极区。 埋地可以在活动单元区域之外的间隔通过连接连接到金属接地线。 使用这种埋地接触消除了对每个电池的单独接地连接的需要，导致电池尺寸的显着降低，并且随之而来的电池密度增加。 本发明的埋地触点可以与各种装置一起使用，包括MRAM和PCRAM装置。

公开(公告)号：US20090218600A1

公开(公告)日：2009-09-03

申请号：US12040227

申请日：2008-02-29

申请人： Human Park ,  Ulrich Klostermann

发明人： Human Park ,  Ulrich Klostermann

IPC分类号： H01L29/76 ,  H01L21/82 ,  G06F17/50

CPC分类号： G06F17/5068 ,  G11C2213/79 ,  H01L27/0207 ,  H01L27/222 ,  H01L27/2436 ,  H01L27/2463 ,  H01L45/06 ,  H01L45/065 ,  H01L45/085 ,  H01L45/141 ,  H01L45/144 ,  H01L45/146 ,  H01L45/148 ,  H01L45/149

摘要： A method for manufacturing an integrated circuit and an integrated circuit are described. In one embodiment, the method for manufacturing the integrated circuit includes determining a layout for numerous memory elements based on memory-specific parameters, and determining a layout for a front-end-of-line (FEOL) component of the integrated circuit based on electrical parameters. Once these two layouts are determined, the layouts are combined to produce a layout for a memory cell on the integrated circuit.

摘要翻译： 对集成电路和集成电路的制造方法进行说明。 在一个实施例中，用于制造集成电路的方法包括基于特定于存储器的参数确定多个存储器元件的布局，以及基于电气的方式确定集成电路的前端（FEOL）部件的布局 参数。 一旦确定了这两个布局，则将布局组合以产生集成电路上的存储器单元的布局。

公开(公告)号：US20070069296A1

公开(公告)日：2007-03-29

申请号：US11369194

申请日：2006-03-06

申请人： Human Park ,  Rainer Leuschner ,  Ulrich Klostermann ,  Richard Ferrant

发明人： Human Park ,  Rainer Leuschner ,  Ulrich Klostermann ,  Richard Ferrant

IPC分类号： H01L27/12

CPC分类号： H01L27/228 ,  B82Y10/00

摘要： A cell design and methods for reducing the cell size of cells in high-current devices, such as MRAM, by increasing the effective width of a transistor in the cell to be greater than the actual width of the active area of the cell are described. This permits the cell size to be decreased without decreasing the current that is driven by the transistor. According to the invention, this is achieved by increasing the length of gate portions of one or more transistors within the active area of a cell to increase the effective transistor width. In one embodiment, two transistors, electrically connected in parallel, are used per cell. The two transistors double the effective transistor width within the cell relative to a single transistor design. Such cell designs can be used with a variety of devices, including various types of MRAM and PCRAM.

摘要翻译： 描述了通过将电池中的晶体管的有效宽度增加到大于电池的有效面积的实际宽度来减小大电流器件（例如MRAM）中的电池单元尺寸的电池设计和方法。 这允许在不降低由晶体管驱动的电流的情况下降低电池尺寸。 根据本发明，这通过增加单元的有效区域内的一个或多个晶体管的栅极部分的长度来增加有效晶体管宽度来实现。 在一个实施例中，每个单元使用并联电连接的两个晶体管。 两个晶体管相对于单晶体管设计，使单元内的有效晶体管宽度倍增。 这样的单元设计可以与各种设备一起使用，包括各种类型的MRAM和PCRAM。

公开(公告)号：US08665629B2

公开(公告)日：2014-03-04

申请号：US11864575

申请日：2007-09-28

申请人： Human Park ,  Ulrich Klostermann ,  Rainer Leuschner

发明人： Human Park ,  Ulrich Klostermann ,  Rainer Leuschner

IPC分类号： G11C11/00

CPC分类号： H01L27/228 ,  H01L27/2436 ,  H01L29/66795 ,  H01L29/785

摘要： An integrated circuit and method for manufacturing an integrated circuit are described. In one embodiment, the integrated circuit includes a memory cell that includes a resistivity changing memory element. The resistivity changing memory element is electrically coupled to a select transistor that includes a FinFET including a source, a drain, and a fin structure formed above a surface of a substrate between the source and the drain. The fin structure includes a channel area extending in a direction substantially parallel to the surface of the substrate, and a dielectric layer formed around at least a portion of the channel area such that an effective channel width of the select transistor depends at least in part on a height of the fin structure.

摘要翻译： 对集成电路的集成电路及其制造方法进行说明。 在一个实施例中，集成电路包括包括电阻率变化存储元件的存储单元。 电阻率变化存储元件电耦合到选择晶体管，该选择晶体管包括在源极和漏极之间形成在衬底表面上方的源极，漏极和鳍状结构的FinFET。 翅片结构包括在基本上平行于衬底的表面的方向上延伸的沟道区，以及围绕沟道区的至少一部分形成的介电层，使得选择晶体管的有效沟道宽度至少部分依赖于 翅片结构的高度。

公开(公告)号：US20090085121A1

公开(公告)日：2009-04-02

申请号：US11864575

申请日：2007-09-28

申请人： Human Park ,  Ulrich Klostermann ,  Rainer Leuschner

发明人： Human Park ,  Ulrich Klostermann ,  Rainer Leuschner

IPC分类号： H01L29/786 ,  H01L21/336

CPC分类号： H01L27/228 ,  H01L27/2436 ,  H01L29/66795 ,  H01L29/785

摘要： An integrated circuit and method for manufacturing an integrated circuit are described. In one embodiment, the integrated circuit includes a memory cell that includes a resistivity changing memory element. The resistivity changing memory element is electrically coupled to a select transistor that includes a FinFET including a source, a drain, and a fin structure formed above a surface of a substrate between the source and the drain. The fin structure includes a channel area extending in a direction substantially parallel to the surface of the substrate, and a dielectric layer formed around at least a portion of the channel area such that an effective channel width of the select transistor depends at least in part on a height of the fin structure.

摘要翻译： 对集成电路的集成电路及其制造方法进行说明。 在一个实施例中，集成电路包括包括电阻率变化存储元件的存储单元。 电阻率变化存储元件电耦合到选择晶体管，该选择晶体管包括在源极和漏极之间形成在衬底表面上方的源极，漏极和鳍状结构的FinFET。 翅片结构包括在基本上平行于衬底的表面的方向上延伸的沟道区，以及围绕沟道区的至少一部分形成的介电层，使得选择晶体管的有效沟道宽度至少部分依赖于 翅片结构的高度。

公开(公告)号：US20070091674A1

公开(公告)日：2007-04-26

申请号：US11536323

申请日：2006-09-28

申请人： Human Park ,  Philippe Blanchard ,  Woosik Kim ,  Gill Lee

发明人： Human Park ,  Philippe Blanchard ,  Woosik Kim ,  Gill Lee

IPC分类号： G11C11/14

CPC分类号： G11C11/16 ,  H01L27/228 ,  H01L27/2436 ,  H01L27/2463 ,  H01L45/06

摘要： A transistor cell and method of making a transistor cell is disclosed. In one embodiment a transistor cell, includes first metal line spacers and the first gate spacers that vertically at least partially overlap, wherein second metal line spacers and second gate spacers vertically at least partially overlap. A contact region is defined above a second source/drain region and/or a third source/drain region by a respective adjacent first metal line spacer and second metal line spacer and by a respective adjacent first gate spacer and second gate spacer. A contact via vertically extends from the contact region at least to the layer of the first metal line.

摘要翻译： 公开了一种制造晶体管单元的晶体管单元和方法。 在一个实施例中，晶体管单元包括第一金属线间隔物和垂直至少部分重叠的第一栅极间隔物，其中第二金属线隔离物和第二栅极间隔物垂直至少部分重叠。 接触区域由相应的相邻的第一金属线间隔物和第二金属线间隔物以及相应的相邻的第一栅极间隔物和第二栅极间隔物限定在第二源极/漏极区域和/或第三源极/漏极区域的上方。 接触孔从接触区域至少垂直地延伸到第一金属线的层。