公开(公告)号：US20080179647A1

公开(公告)日：2008-07-31

申请号：US11964146

申请日：2007-12-26

申请人： Hyeoung-won Seo ,  Dong-hyun Kim ,  Kang-yoon Lee ,  Seong-goo Kim

发明人： Hyeoung-won Seo ,  Dong-hyun Kim ,  Kang-yoon Lee ,  Seong-goo Kim

IPC分类号： H01L27/108 ,  H01L21/8239

CPC分类号： H01L27/10885 ,  H01L27/10814 ,  H01L27/10823 ,  H01L27/10876

摘要： A semiconductor device comprising a barrier insulating layer and a related method of fabrication is disclosed. The semiconductor device semiconductor substrate includes a plurality of active regions, wherein active regions are defined by a device isolation layer and are disposed along a first direction; a plurality of bit line electrodes connected to the active regions, wherein each of the bit line electrodes extends along a second direction; and a plurality of first barrier insulating layers. Each of the first barrier insulating layers extends along a third direction, at least one of the first barrier insulating layers is disposed on a corresponding first portion of the device isolation layer disposed between two of the active regions, the two of the active regions are adjacent along the first direction, and the first direction and the second direction differ from one another.

摘要翻译： 公开了一种包括阻挡绝缘层和相关制造方法的半导体器件。 半导体器件半导体衬底包括多个有源区，其中有源区由器件隔离层限定，并沿着第一方向设置; 连接到有源区的多个位线电极，其中每个位线电极沿着第二方向延伸; 以及多个第一阻挡绝缘层。 每个第一阻挡绝缘层沿着第三方向延伸，至少一个第一阻挡绝缘层设置在设置在两个有源区之间的器件隔离层的对应的第一部分上，两个有源区相邻 沿第一方向，第一方向和第二方向彼此不同。

公开(公告)号：US08283714B2

公开(公告)日：2012-10-09

申请号：US13085898

申请日：2011-04-13

申请人： Hyeoung-won Seo ,  Bong-soo Kim ,  Dong-gun Park ,  Kang-yoon Lee ,  Jae-man Yoon ,  Seong-goo Kim ,  Seung-bae Park

发明人： Hyeoung-won Seo ,  Bong-soo Kim ,  Dong-gun Park ,  Kang-yoon Lee ,  Jae-man Yoon ,  Seong-goo Kim ,  Seung-bae Park

IPC分类号： H01L29/94

CPC分类号： H01L27/0207 ,  H01L27/10814 ,  H01L27/10823 ,  H01L27/10876 ,  H01L27/10888 ,  H01L27/10891

摘要： Channels of two transistors are vertically formed on portions of two opposite side surfaces of one active region, and gate electrodes are vertically formed on a device isolation layer contacting the channels of the active region. A common bit line contact plug is formed in the central portions of the active region, two storage node contact plugs are formed on both sides of the bit line contact plug, and an insulating spacer is formed on a side surface of the bit line contact plug. A word line, a bit line, and a capacitor are sequentially stacked on the semiconductor substrate, like a conventional semiconductor memory device. Thus, effective space arrangement of a memory cell is possible such that a 4F2 structure is constituted, and a conventional line and contact forming process can be applied such that highly integrated semiconductor memory device is readily fabricated.

摘要翻译： 两个晶体管的沟道垂直地形成在一个有源区的两个相对的侧表面的部分上，并且栅极垂直地形成在与有源区的沟道接触的器件隔离层上。 在有源区域的中心部分形成共同的位线接触插塞，在位线接触插塞的两侧形成两个存储节点接触插塞，并且在位线接触插头的侧面上形成绝缘间隔件 。 像现有的半导体存储器件一样，在半导体衬底上顺序层叠字线，位线和电容器。 因此，存储单元的有效空间布置是可能的，使得构成4F2结构，并且可以应用常规的线和接触形成工艺，从而容易地制造高度集成的半导体存储器件。

公开(公告)号：US20080211013A1

公开(公告)日：2008-09-04

申请号：US12118268

申请日：2008-05-09

申请人： Hyeoung-won Seo ,  Jae-man Yoon ,  Kang-yoon Lee ,  Dong-gun Park ,  Bong-soo Kim ,  Seong-goo Kim

发明人： Hyeoung-won Seo ,  Jae-man Yoon ,  Kang-yoon Lee ,  Dong-gun Park ,  Bong-soo Kim ,  Seong-goo Kim

IPC分类号： H01L29/78

CPC分类号： H01L29/66666 ,  H01L27/0207 ,  H01L27/10814 ,  H01L27/10823 ,  H01L27/10876 ,  H01L27/10885 ,  H01L27/10891 ,  H01L29/7827

摘要： In a semiconductor memory device having a vertical channel transistor a body of which is connected to a substrate and a method of fabricating the same, the semiconductor memory device includes a semiconductor substrate including a plurality of pillars arranged spaced apart from one another, and each of the pillars includes a body portion and a pair of pillar portions extending from the body portion and spaced apart from each other. A gate electrode is formed to surround each of the pillar portions. A bitline is disposed on the body portion to penetrate a region between a pair of the pillar portions of each of the first pillars arranged to extend in a first direction. A wordline is disposed over the bitline, arranged to extend in a second direction intersecting the first direction, and configured to contact the side surface of the gate electrode. A first doped region is formed in the upper surface of each of the pillar portions of the pillar. A second doped region is formed on the body portion of the pillar and connected electrically to the bitline. Storage node electrodes are connected electrically to the first doped region and disposed on each of the pillar portions.

摘要翻译： 在具有其主体连接到基板的垂直沟道晶体管的半导体存储器件及其制造方法中，半导体存储器件包括：半导体衬底，其包括彼此间隔布置的多个柱，并且每个 支柱包括主体部分和从主体部分延伸并彼此间隔开的一对柱部分。 形成围绕每个支柱部分的栅电极。 位于所述主体部分上的位线穿过所述第一支柱中的所述第一支柱的一对支柱之间的区域，所述第一支柱布置成沿第一方向延伸。 字线布置在位线之外，布置成沿与第一方向相交的第二方向延伸，并且被配置为接触栅电极的侧表面。 第一掺杂区域形成在柱的每个柱部分的上表面中。 第二掺杂区形成在柱的主体部分上并与电位线连接。 存储节点电极与第一掺杂区域电连接并设置在每个柱部分上。

公开(公告)号：US20110186923A1

公开(公告)日：2011-08-04

申请号：US13085898

申请日：2011-04-13

申请人： Hyeoung-won Seo ,  Bong-soo Kim ,  Dong-gun Park ,  Kang-yoon Lee ,  Jae-man Yoon ,  Seong-goo Kim ,  Seung-bae Park

发明人： Hyeoung-won Seo ,  Bong-soo Kim ,  Dong-gun Park ,  Kang-yoon Lee ,  Jae-man Yoon ,  Seong-goo Kim ,  Seung-bae Park

IPC分类号： H01L29/78

CPC分类号： H01L27/0207 ,  H01L27/10814 ,  H01L27/10823 ,  H01L27/10876 ,  H01L27/10888 ,  H01L27/10891

摘要： Channels of two transistors are vertically formed on portions of two opposite side surfaces of one active region, and gate electrodes are vertically formed on a device isolation layer contacting the channels of the active region. A common bit line contact plug is formed in the central portions of the active region, two storage node contact plugs are formed on both sides of the bit line contact plug, and an insulating spacer is formed on a side surface of the bit line contact plug. A word line, a bit line, and a capacitor are sequentially stacked on the semiconductor substrate, like a conventional semiconductor memory device. Thus, effective space arrangement of a memory cell is possible such that a 4F2 structure is constituted, and a conventional line and contact forming process can be applied such that highly integrated semiconductor memory device is readily fabricated

摘要翻译： 两个晶体管的沟道垂直地形成在一个有源区的两个相对的侧表面的部分上，并且栅极垂直地形成在与有源区的沟道接触的器件隔离层上。 在有源区域的中心部分形成共同的位线接触插塞，在位线接触插塞的两侧形成两个存储节点接触插塞，并且在位线接触插头的侧面上形成绝缘间隔件 。 像现有的半导体存储器件一样，在半导体衬底上顺序层叠字线，位线和电容器。 因此，存储单元的有效空间布置是可能的，使得构成4F2结构，并且可以应用常规的线和接触形成工艺，使得容易制造高度集成的半导体存储器件

公开(公告)号：US07387931B2

公开(公告)日：2008-06-17

申请号：US11546581

申请日：2006-10-11

申请人： Hyeoung-won Seo ,  Jae-man Yoon ,  Kang-yoon Lee ,  Dong-gun Park ,  Bong-soo Kim ,  Seong-goo Kim

发明人： Hyeoung-won Seo ,  Jae-man Yoon ,  Kang-yoon Lee ,  Dong-gun Park ,  Bong-soo Kim ,  Seong-goo Kim

IPC分类号： H01L21/8242 ,  H01L21/336

CPC分类号： H01L29/66666 ,  H01L27/0207 ,  H01L27/10814 ,  H01L27/10823 ,  H01L27/10876 ,  H01L27/10885 ,  H01L27/10891 ,  H01L29/7827

摘要： In a semiconductor memory device having a vertical channel transistor a body of which is connected to a substrate and a method of fabricating the same, the semiconductor memory device includes a semiconductor substrate including a plurality of pillars arranged spaced apart from one another, and each of the pillars includes a body portion and a pair of pillar portions extending from the body portion and spaced apart from each other. A gate electrode is formed to surround each of the pillar portions. A bitline is disposed on the body portion to penetrate a region between a pair of the pillar portions of each of the first pillars arranged to extend in a first direction. A wordline is disposed over the bitline, arranged to extend in a second direction intersecting the first direction, and configured to contact the side surface of the gate electrode. A first doped region is formed in the upper surface of each of the pillar portions of the pillar. A second doped region is formed on the body portion of the pillar and connected electrically to the bitline. Storage node electrodes are connected electrically to the first doped region and disposed on each of the pillar portions.

摘要翻译： 在具有其主体连接到基板的垂直沟道晶体管的半导体存储器件及其制造方法中，半导体存储器件包括：半导体衬底，其包括彼此间隔布置的多个柱，并且每个 支柱包括主体部分和从主体部分延伸并彼此间隔开的一对柱部分。 形成围绕每个支柱部分的栅电极。 位于所述主体部分上的位线穿过所述第一支柱中的所述第一支柱的一对支柱之间的区域，所述第一支柱布置成沿第一方向延伸。 字线布置在位线之外，布置成沿与第一方向相交的第二方向延伸，并且被配置为接触栅电极的侧表面。 第一掺杂区域形成在柱的每个柱部分的上表面中。 第二掺杂区形成在柱的主体部分上并与电位线连接。 存储节点电极与第一掺杂区域电连接并设置在每个柱部分上。

公开(公告)号：US20120273898A1

公开(公告)日：2012-11-01

申请号：US13549648

申请日：2012-07-16

申请人： Hyeoung-won Seo ,  Bong-soo Kim ,  Dong-gun Park ,  Kang-yoon Lee ,  Jae-man Yoon ,  Seong-goo Kim ,  Seung-bae Park

发明人： Hyeoung-won Seo ,  Bong-soo Kim ,  Dong-gun Park ,  Kang-yoon Lee ,  Jae-man Yoon ,  Seong-goo Kim ,  Seung-bae Park

IPC分类号： H01L27/088

CPC分类号： H01L27/0207 ,  H01L27/10814 ,  H01L27/10823 ,  H01L27/10876 ,  H01L27/10888 ,  H01L27/10891

摘要： Channels of two transistors are vertically formed on portions of two opposite side surfaces of one active region, and gate electrodes are vertically formed on a device isolation layer contacting the channels of the active region. A common bit line contact plug is formed in the central portions of the active region, two storage node contact plugs are formed on both sides of the bit line contact plug, and an insulating spacer is formed on a side surface of the bit line contact plug. A word line, a bit line, and a capacitor are sequentially stacked on the semiconductor substrate, like a conventional semiconductor memory device. Thus, effective space arrangement of a memory cell is possible such that a 4F2 structure is constituted, and a conventional line and contact forming process can be applied such that highly integrated semiconductor memory device is readily fabricated

摘要翻译： 两个晶体管的沟道垂直地形成在一个有源区的两个相对的侧表面的部分上，并且栅极垂直地形成在与有源区的沟道接触的器件隔离层上。 在有源区域的中心部分形成共同的位线接触插塞，在位线接触插塞的两侧形成两个存储节点接触插塞，并且在位线接触插头的侧面上形成绝缘间隔件 。 像现有的半导体存储器件一样，在半导体衬底上顺序层叠字线，位线和电容器。 因此，存储单元的有效空间布置是可能的，使得构成4F2结构，并且可以应用常规的线和接触形成工艺，使得容易制造高度集成的半导体存储器件

公开(公告)号：US08039896B2

公开(公告)日：2011-10-18

申请号：US12118268

申请日：2008-05-09

申请人： Hyeoung-won Seo ,  Jae-man Yoon ,  Kang-yoon Lee ,  Dong-gun Park ,  Bong-soo Kim ,  Seong-goo Kim

发明人： Hyeoung-won Seo ,  Jae-man Yoon ,  Kang-yoon Lee ,  Dong-gun Park ,  Bong-soo Kim ,  Seong-goo Kim

IPC分类号： H01L29/66

CPC分类号： H01L29/66666 ,  H01L27/0207 ,  H01L27/10814 ,  H01L27/10823 ,  H01L27/10876 ,  H01L27/10885 ,  H01L27/10891 ,  H01L29/7827

摘要： In a semiconductor memory device having a vertical channel transistor a body of which is connected to a substrate and a method of fabricating the same, the semiconductor memory device includes a semiconductor substrate including a plurality of pillars arranged spaced apart from one another, and each of the pillars includes a body portion and a pair of pillar portions extending from the body portion and spaced apart from each other. A gate electrode is formed to surround each of the pillar portions. A bitline is disposed on the body portion to penetrate a region between a pair of the pillar portions of each of the first pillars arranged to extend in a first direction. A wordline is disposed over the bitline, arranged to extend in a second direction intersecting the first direction, and configured to contact the side surface of the gate electrode. A first doped region is formed in the upper surface of each of the pillar portions of the pillar. A second doped region is formed on the body portion of the pillar and connected electrically to the bitline. Storage node electrodes are connected electrically to the first doped region and disposed on each of the pillar portions.

摘要翻译： 在具有其主体连接到基板的垂直沟道晶体管的半导体存储器件及其制造方法中，半导体存储器件包括：半导体衬底，其包括彼此间隔布置的多个柱，并且每个 支柱包括主体部分和从主体部分延伸并彼此间隔开的一对柱部分。 形成围绕每个支柱部分的栅电极。 位于所述主体部分上的位线穿过所述第一支柱中的所述第一支柱的一对支柱之间的区域，所述第一支柱布置成沿第一方向延伸。 字线布置在位线之外，布置成沿与第一方向相交的第二方向延伸，并且被配置为接触栅电极的侧表面。 第一掺杂区域形成在柱的每个柱部分的上表面中。 第二掺杂区形成在柱的主体部分上并与电位线连接。 存储节点电极与第一掺杂区域电连接并设置在每个柱部分上。

公开(公告)号：US08022457B2

公开(公告)日：2011-09-20

申请号：US11600568

申请日：2006-11-16

申请人： Hyeoung-won Seo ,  Bong-soo Kim ,  Dong-gun Park ,  Kang-yoon Lee ,  Jae-man Yoon ,  Seong-goo Kim ,  Seung-bae Park

发明人： Hyeoung-won Seo ,  Bong-soo Kim ,  Dong-gun Park ,  Kang-yoon Lee ,  Jae-man Yoon ,  Seong-goo Kim ,  Seung-bae Park

IPC分类号： H01L29/94

CPC分类号： H01L27/0207 ,  H01L27/10814 ,  H01L27/10823 ,  H01L27/10876 ,  H01L27/10888 ,  H01L27/10891

摘要： Channels of two transistors are vertically formed on portions of two opposite side surfaces of one active region, and gate electrodes are vertically formed on a device isolation layer contacting the channels of the active region. A common bit line contact plug is formed in the central portions of the active region, two storage node contact plugs are formed on both sides of the bit line contact plug, and an insulating spacer is formed on a side surface of the bit line contact plug. A word line, a bit line, and a capacitor are sequentially stacked on the semiconductor substrate, like a conventional semiconductor memory device. Thus, effective space arrangement of a memory cell is possible such that a 4F2 structure is constituted, and a conventional line and contact forming process can be applied such that highly integrated semiconductor memory device is readily fabricated.

摘要翻译： 两个晶体管的沟道垂直地形成在一个有源区的两个相对的侧表面的部分上，并且栅极垂直地形成在与有源区的沟道接触的器件隔离层上。 在有源区域的中心部分形成共同的位线接触插塞，在位线接触插塞的两侧形成两个存储节点接触插塞，并且在位线接触插头的侧面上形成绝缘间隔件 。 像现有的半导体存储器件一样，在半导体衬底上顺序层叠字线，位线和电容器。 因此，存储单元的有效空间布置是可能的，使得构成4F2结构，并且可以应用常规的线和接触形成工艺，从而容易地制造高度集成的半导体存储器件。

公开(公告)号：US07368352B2

公开(公告)日：2008-05-06

申请号：US11479462

申请日：2006-06-30

申请人： Bong-soo Kim ,  Jae-man Yoon ,  Seong-goo Kim ,  Hyeoung-won Seo ,  Dong-gun Park ,  Kang-yoon Lee

发明人： Bong-soo Kim ,  Jae-man Yoon ,  Seong-goo Kim ,  Hyeoung-won Seo ,  Dong-gun Park ,  Kang-yoon Lee

IPC分类号： H01L21/8234 ,  H01L21/8244 ,  H01L21/336

CPC分类号： H01L29/66666 ,  H01L27/10876 ,  H01L27/10885

摘要： In a semiconductor device and a method of fabricating the same, a vertical channel transistor has a cell occupation area of 4F2. The semiconductor device comprises: a cell array region having a plurality of unit cells, each unit cell having a cell occupation area, repeatedly aligned along a first direction and along a second direction, the first and second directions being perpendicular to each other in a horizontal direction along a primary surface of a semiconductor substrate, wherein each unit cell has a uniform first pitch in the first direction and in the second direction; an active pillar vertically extending from an active region of each unit cell integrally with the semiconductor substrate in a vertical direction that is perpendicular with respect to the primary surface of the semiconductor substrate, wherein widths of at least a portion of the active pillar in the first direction and in the second direction are equal to a first width 1F as a minimum feature size in the cell array region; a ring-shaped gate surrounding a sidewall of the active pillar; a channel region formed to extend along the active pillar in the vertical direction; a buried bit line formed below the active pillar in the semiconductor substrate; and a word line extending in the horizontal direction perpendicular to the buried bit line, and electrically connected to the ring-shaped gate, wherein a distance from the active pillar of any one unit cell of the plurality of unit cells to each of the active pillars of nearest neighboring unit cells in the first direction and the second direction is equal to the first width of the active pillar of one unit cell.

摘要翻译： 在半导体器件及其制造方法中，垂直沟道晶体管具有4F 2的单元占用面积。 半导体器件包括：具有多个单元的单元阵列区域，每个单位单元具有单元占用面积，沿着第一方向并沿第二方向重复排列，所述第一和第二方向在水平方向彼此垂直 沿着半导体基板的主表面的方向，其中每个单元电池在第一方向和第二方向具有均匀的第一间距; 在与所述半导体衬底的所述主表面垂直的垂直方向上从所述每个单电池的有源区域与所述半导体衬底一体地垂直延伸的有源柱，其中，所述有源柱的至少一部分的宽度在所述第一 方向和第二方向等于作为单元阵列区域中的最小特征尺寸的第一宽度1F; 围绕有源柱的侧壁的环形门; 形成为沿所述有源柱沿垂直方向延伸的沟道区域; 形成在半导体衬底中的有源柱下方的掩埋位线; 以及在垂直于掩埋位线的水平方向上延伸并且与环状栅极电连接的字线，其中从多个单元电池中的任何一个单电池的有源支柱到每个有源支柱的距离 在第一方向和第二方向上的最近相邻单位单元的像素等于一个单位单元的有源柱的第一宽度。

公开(公告)号：US20070075359A1

公开(公告)日：2007-04-05

申请号：US11541756

申请日：2006-10-02

申请人： Jae-man Yoon ,  Dong-gun Park ,  Kang-yoon Lee ,  Choong-ho Lee ,  Bong-soo Kim ,  Seong-goo Kim ,  Hyeoung-won Seo ,  Seung-bae Park

发明人： Jae-man Yoon ,  Dong-gun Park ,  Kang-yoon Lee ,  Choong-ho Lee ,  Bong-soo Kim ,  Seong-goo Kim ,  Hyeoung-won Seo ,  Seung-bae Park

IPC分类号： H01L21/8238

CPC分类号： H01L29/66666 ,  H01L21/823885 ,  H01L27/10876 ,  H01L27/10885 ,  H01L27/10894 ,  H01L29/7827 ,  H01L2924/0002 ,  H01L2924/00

摘要： In a circuit device including vertical transistors connected to buried bitlines and a method of manufacturing the circuit device, the circuit device includes a semiconductor substrate including a peripheral circuit region and left and right cell regions at both sides of the peripheral circuit region; bottom active regions arranged on the semiconductor substrate to be spaced apart from one another in a column direction and to extend from the peripheral circuit region alternately to the left cell region and the right cell region in a row direction; channel pillars protruding from the bottom active regions in a vertical direction and arranged to be aligned in the row direction and spaced apart from one another; gate electrodes provided with a gate dielectric layer and attached to surround side surfaces of the channel pillars; buried bitlines extending along the bottom active regions, the bottom active regions including a bottom source/drain region; local interconnection lines contacting side surfaces of the gate electrodes in the peripheral circuit region and extending between the gate electrodes to commonly interconnect the gate electrodes in the peripheral circuit region, thereby configuring a peripheral circuit; signal lines electrically connected to upper surfaces of the channel pillars or to at least one of the local interconnection lines; and interconnection contacts electrically connecting the local interconnection line to the buried bitline of a different row from that of the commonly-connected gate electrodes or electrically connecting the local interconnection lines to the signal lines, thereby configuring the peripheral circuit.

摘要翻译： 在包括连接到掩埋位线的垂直晶体管的电路器件和制造电路器件的方法中，电路器件包括半导体衬底，该半导体衬底包括外围电路区域和外围电路区域两侧的左右单元区域; 布置在半导体衬底上的底部有源区域在列方向上彼此间隔开并且从外围电路区域交替地延伸到左小区区域和右小区区域在行方向上延伸; 通道柱从垂直方向从底部有源区域突出并且布置成在行方向上对齐并且彼此间隔开; 栅极电极设置有栅极电介质层并附接到环绕通道柱的侧表面; 掩埋位线沿着底部有源区延伸，底部有源区域包括底部源极/漏极区域; 局部互连线与外围电路区域中的栅电极的侧表面接触并在栅电极之间延伸，以在外围电路区域中共同连接栅电极，从而构成外围电路; 信号线电连接到通道柱的上表面或至少一个局部互连线; 以及互连触点将本地互连线电连接到与共用栅极电极的不同行的掩埋位线或将本地互连线电连接到信号线，从而配置外围电路。