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    Circuit device including vertical transistors connected to buried bitlines and method of manufacturing the same
    1.
    发明申请
    Circuit device including vertical transistors connected to buried bitlines and method of manufacturing the same 有权
    电路装置包括连接到埋地位线的垂直晶体管及其制造方法

    公开(公告)号：US20070075359A1

    公开(公告)日：2007-04-05

    申请号：US11541756

    申请日：2006-10-02

    申请人： Jae-man Yoon ,  Dong-gun Park ,  Kang-yoon Lee ,  Choong-ho Lee ,  Bong-soo Kim ,  Seong-goo Kim ,  Hyeoung-won Seo ,  Seung-bae Park

    发明人： Jae-man Yoon ,  Dong-gun Park ,  Kang-yoon Lee ,  Choong-ho Lee ,  Bong-soo Kim ,  Seong-goo Kim ,  Hyeoung-won Seo ,  Seung-bae Park

    IPC分类号： H01L21/8238

    CPC分类号： H01L29/66666 ,  H01L21/823885 ,  H01L27/10876 ,  H01L27/10885 ,  H01L27/10894 ,  H01L29/7827 ,  H01L2924/0002 ,  H01L2924/00

    摘要： In a circuit device including vertical transistors connected to buried bitlines and a method of manufacturing the circuit device, the circuit device includes a semiconductor substrate including a peripheral circuit region and left and right cell regions at both sides of the peripheral circuit region; bottom active regions arranged on the semiconductor substrate to be spaced apart from one another in a column direction and to extend from the peripheral circuit region alternately to the left cell region and the right cell region in a row direction; channel pillars protruding from the bottom active regions in a vertical direction and arranged to be aligned in the row direction and spaced apart from one another; gate electrodes provided with a gate dielectric layer and attached to surround side surfaces of the channel pillars; buried bitlines extending along the bottom active regions, the bottom active regions including a bottom source/drain region; local interconnection lines contacting side surfaces of the gate electrodes in the peripheral circuit region and extending between the gate electrodes to commonly interconnect the gate electrodes in the peripheral circuit region, thereby configuring a peripheral circuit; signal lines electrically connected to upper surfaces of the channel pillars or to at least one of the local interconnection lines; and interconnection contacts electrically connecting the local interconnection line to the buried bitline of a different row from that of the commonly-connected gate electrodes or electrically connecting the local interconnection lines to the signal lines, thereby configuring the peripheral circuit.

    摘要翻译： 在包括连接到掩埋位线的垂直晶体管的电路器件和制造电路器件的方法中，电路器件包括半导体衬底，该半导体衬底包括外围电路区域和外围电路区域两侧的左右单元区域; 布置在半导体衬底上的底部有源区域在列方向上彼此间隔开并且从外围电路区域交替地延伸到左小区区域和右小区区域在行方向上延伸; 通道柱从垂直方向从底部有源区域突出并且布置成在行方向上对齐并且彼此间隔开; 栅极电极设置有栅极电介质层并附接到环绕通道柱的侧表面; 掩埋位线沿着底部有源区延伸，底部有源区域包括底部源极/漏极区域; 局部互连线与外围电路区域中的栅电极的侧表面接触并在栅电极之间延伸，以在外围电路区域中共同连接栅电极，从而构成外围电路; 信号线电连接到通道柱的上表面或至少一个局部互连线; 以及互连触点将本地互连线电连接到与共用栅极电极的不同行的掩埋位线或将本地互连线电连接到信号线，从而配置外围电路。

    Circuit device including vertical transistors connected to buried bitlines and method of manufacturing the same
    2.
    发明授权
    Circuit device including vertical transistors connected to buried bitlines and method of manufacturing the same 有权
    电路装置包括连接到埋地位线的垂直晶体管及其制造方法

    公开(公告)号：US07586149B2

    公开(公告)日：2009-09-08

    申请号：US11541756

    申请日：2006-10-02

    申请人： Jae-man Yoon ,  Dong-gun Park ,  Kang-yoon Lee ,  Choong-ho Lee ,  Bong-soo Kim ,  Seong-goo Kim ,  Hyeoung-won Seo ,  Seung-bae Park

    发明人： Jae-man Yoon ,  Dong-gun Park ,  Kang-yoon Lee ,  Choong-ho Lee ,  Bong-soo Kim ,  Seong-goo Kim ,  Hyeoung-won Seo ,  Seung-bae Park

    IPC分类号： H01L23/528 ,  H01L27/108

    CPC分类号： H01L29/66666 ,  H01L21/823885 ,  H01L27/10876 ,  H01L27/10885 ,  H01L27/10894 ,  H01L29/7827 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A circuit device including vertical transistors connected to buried bitlines and a method of manufacturing the circuit device. The circuit device includes a semiconductor substrate including a peripheral circuit region and left and right cell regions at both sides of the peripheral circuit region, bottom active regions arranged on the semiconductor substrate to be spaced apart from one another in a column direction and to extend from the peripheral circuit region alternately to the left cell region and the right cell region in a row direction, channel pillars protruding from the bottom active regions in a vertical direction and arranged to be aligned in the row direction and spaced apart from one another, gate electrodes provided with a gate dielectric layer and attached to surround side surfaces of the channel pillars, and buried bitlines extending along the bottom active regions, the bottom active regions including a bottom source/drain region.

    摘要翻译： 一种包括连接到掩埋位线的垂直晶体管的电路器件和制造该电路器件的方法。 该电路装置包括半导体衬底，该半导体衬底包括外围电路区域和在外围电路区域的两侧的左侧和右侧电池区域，布置在半导体衬底上的底部有源区域在列方向上彼此间隔开并从 所述外围电路区域与所述左侧单元区域和右侧单元区域交替地排列成行方向，所述通道柱从所述底部有源区域沿垂直方向突出并且被配置为在所述行方向上彼此对准并且彼此间隔开，栅电极 设置有栅介电层并且被附接到环绕通道柱的侧表面，以及沿底部有源区延伸的掩埋位线，底部有源区包括底部源极/漏极区。

    Semiconductor memory devices including a vertical channel transistor having a buried bit line
    3.
    发明授权
    Semiconductor memory devices including a vertical channel transistor having a buried bit line 有权
    半导体存储器件包括具有埋入位线的垂直沟道晶体管

    公开(公告)号：US08154065B2

    公开(公告)日：2012-04-10

    申请号：US12418879

    申请日：2009-04-06

    申请人： Jae-man Yoon ,  Dong-gun Park ,  Choong-ho Lee ,  Moon-suk Yi ,  Chul Lee

    发明人： Jae-man Yoon ,  Dong-gun Park ,  Choong-ho Lee ,  Moon-suk Yi ,  Chul Lee

    IPC分类号： H01L27/108

    CPC分类号： H01L27/10885 ,  H01L27/0207 ,  H01L27/10814 ,  H01L27/10876 ,  H01L29/66666

    摘要： Semiconductor memory devices include a semiconductor substrate and a plurality of semiconductor material pillars in a spaced relationship on the semiconductor substrate. Respective surrounding gate electrodes surround ones of the pillars. A first source/drain region is in the semiconductor substrate between adjacent ones of the pillars and a second source/drain region is in an upper portion of at least one of the adjacent pillars. A buried bit line is in the first source/drain region and electrically coupled to the first source/drain region and a storage node electrode is on the upper portion of the at least one of the adjacent pillars and electrically contacting with the second source/drain region.

    摘要翻译： 半导体存储器件包括在半导体衬底上具有间隔关系的半导体衬底和多个半导体材料柱。 相邻的围绕电极围绕其中的一个柱。 第一源极/漏极区域在相邻的柱之间的半导体衬底中，并且第二源极/漏极区域位于至少一个相邻支柱的上部。 掩埋位线在第一源极/漏极区域中并且电耦合到第一源极/漏极区域，并且存储节点电极在相邻柱的至少一个的上部上并且与第二源极/漏极 地区。

    Semiconductor Memory Devices Including a Vertical Channel Transistor
    4.
    发明申请
    Semiconductor Memory Devices Including a Vertical Channel Transistor 有权
    包括垂直通道晶体管的半导体存储器件

    公开(公告)号：US20090189217A1

    公开(公告)日：2009-07-30

    申请号：US12418879

    申请日：2009-04-06

    申请人： Jae-man Yoon ,  Dong-gun Park ,  Choong-ho Lee ,  Moon-suk Yi ,  Chul Lee

    发明人： Jae-man Yoon ,  Dong-gun Park ,  Choong-ho Lee ,  Moon-suk Yi ,  Chul Lee

    IPC分类号： H01L29/78

    CPC分类号： H01L27/10885 ,  H01L27/0207 ,  H01L27/10814 ,  H01L27/10876 ,  H01L29/66666

    摘要： Semiconductor memory devices include a semiconductor substrate and a plurality of semiconductor material pillars in a spaced relationship on the semiconductor substrate. Respective surrounding gate electrodes surround ones of the pillars. A first source/drain region is in the semiconductor substrate between adjacent ones of the pillars and a second source/drain region is in an upper portion of at least one of the adjacent pillars. A buried bit line is in the first source/drain region and electrically coupled to the first source/drain region and a storage node electrode is on the upper portion of the at least one of the adjacent pillars and electrically contacting with the second source/drain region.

    摘要翻译： 半导体存储器件包括在半导体衬底上具有间隔关系的半导体衬底和多个半导体材料柱。 相邻的围绕电极围绕其中的一个柱。 第一源极/漏极区域在相邻的柱之间的半导体衬底中，并且第二源极/漏极区域位于至少一个相邻支柱的上部。 掩埋位线在第一源极/漏极区域中并且电耦合到第一源极/漏极区域，并且存储节点电极在相邻柱的至少一个的上部上并且与第二源极/漏极 地区。

    Semiconductor memory devices including a vertical channel transistor and methods of manufacturing the same
    7.
    发明申请
    Semiconductor memory devices including a vertical channel transistor and methods of manufacturing the same 有权
    包括垂直沟道晶体管的半导体存储器件及其制造方法

    公开(公告)号：US20060097304A1

    公开(公告)日：2006-05-11

    申请号：US11151673

    申请日：2005-06-13

    申请人： Jae-man Yoon ,  Dong-gun Park ,  Choong-ho Lee ,  Moon-suk Yi ,  Chul Lee

    发明人： Jae-man Yoon ,  Dong-gun Park ,  Choong-ho Lee ,  Moon-suk Yi ,  Chul Lee

    IPC分类号： H01L29/94 ,  H01L21/20

    CPC分类号： H01L27/10885 ,  H01L27/0207 ,  H01L27/10814 ,  H01L27/10876 ,  H01L29/66666

    摘要： Semiconductor memory devices include a semiconductor substrate and a plurality of semiconductor material pillars in a spaced relationship on the semiconductor substrate. Respective surrounding gate electrodes surround ones of the pillars. A first source/drain region is in the semiconductor substrate between adjacent ones of the pillars and a second source/drain region is in an upper portion of at least one of the adjacent pillars. A buried bit line is in the first source/drain region and electrically coupled to the first source/drain region and a storage node electrode is on the upper portion of the at least one of the adjacent pillars and electrically contacting with the second source/drain region.

    摘要翻译： 半导体存储器件包括在半导体衬底上具有间隔关系的半导体衬底和多个半导体材料柱。 相邻的围绕电极围绕其中的一个柱。 第一源极/漏极区域在相邻的柱之间的半导体衬底中，并且第二源极/漏极区域位于至少一个相邻支柱的上部。 掩埋位线在第一源极/漏极区域中并且电耦合到第一源极/漏极区域，并且存储节点电极在相邻柱的至少一个的上部上并且与第二源极/漏极 地区。

    Methods of manufacturing semiconductor memory devices including a vertical channel transistor
    8.
    发明授权
    Methods of manufacturing semiconductor memory devices including a vertical channel transistor 有权
    制造包括垂直沟道晶体管的半导体存储器件的方法

    公开(公告)号：US07531412B2

    公开(公告)日：2009-05-12

    申请号：US11151673

    申请日：2005-06-13

    申请人： Jae-man Yoon ,  Dong-gun Park ,  Choong-ho Lee ,  Moon-suk Yi ,  Chul Lee

    发明人： Jae-man Yoon ,  Dong-gun Park ,  Choong-ho Lee ,  Moon-suk Yi ,  Chul Lee

    IPC分类号： H01L21/336

    CPC分类号： H01L27/10885 ,  H01L27/0207 ,  H01L27/10814 ,  H01L27/10876 ,  H01L29/66666

    摘要： Semiconductor memory devices include a semiconductor substrate and a plurality of semiconductor material pillars in a spaced relationship on the semiconductor substrate. Respective surrounding gate electrodes surround ones of the pillars. A first source/drain region is in the semiconductor substrate between adjacent ones of the pillars and a second source/drain region is in an upper portion of at least one of the adjacent pillars. A buried bit line is in the first source/drain region and electrically coupled to the first source/drain region and a storage node electrode is on the upper portion of the at least one of the adjacent pillars and electrically contacting with the second source/drain region.

    摘要翻译： 半导体存储器件包括在半导体衬底上具有间隔关系的半导体衬底和多个半导体材料柱。 相邻的围绕电极围绕其中的一个柱。 第一源极/漏极区域在相邻的柱之间的半导体衬底中，并且第二源极/漏极区域位于至少一个相邻支柱的上部。 掩埋位线在第一源极/漏极区域中并且电耦合到第一源极/漏极区域，并且存储节点电极在相邻柱的至少一个的上部上并且与第二源极/漏极 地区。

    Method of manufacturing semiconductor device having notched gate MOSFET
    10.
    发明授权
    Method of manufacturing semiconductor device having notched gate MOSFET 有权
    具有开槽栅极MOSFET的半导体器件的制造方法

    公开(公告)号：US08044451B2

    公开(公告)日：2011-10-25

    申请号：US12498615

    申请日：2009-07-07

    申请人： Byung-yong Choi ,  Choong-ho Lee ,  Dong-won Kim ,  Dong-gun Park

    发明人： Byung-yong Choi ,  Choong-ho Lee ,  Dong-won Kim ,  Dong-gun Park

    IPC分类号： H01L29/788

    CPC分类号： H01L21/26586 ,  H01L29/665 ,  H01L29/66537 ,  H01L29/66553 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66621 ,  H01L29/7833 ,  H01L29/7834

    摘要： Provided is a method of manufacturing a semiconductor device, by which a cell transistor formed on a cell array area of a semiconductor substrate employs a structure in which an electrode in the shape of spacers is used to form a gate and a multi-bit operation is possible using localized bits, and transistors having structures optimized to satisfy different requirements depending upon functions of the transistors can be formed on a peripheral circuit area which is the residual area of the semiconductor substrate. In this method, a cell transistor is formed on the cell array area. The cell transistor includes a notch gate structure, a first channel region formed on a semiconductor substrate under the notch gate structure, a source region and a drain region formed on both sides of the first channel region, a first gate insulation film formed between the first channel region and the notch gate structure, and a memory layer locally formed on areas adjacent to the source and drain regions between the first channel region and the notch gate structure. At the same time that the cell transistor is formed, a plurality of peripheral circuit transistors including at least one transistor having a different structure from the cell transistor are formed on the peripheral circuit area.

    摘要翻译： 提供一种制造半导体器件的方法，通过该方法，形成在半导体衬底的单元阵列区域上的单元晶体管采用其中使用间隔物形状的电极形成栅极并且多位操作是 可能使用局部位，并且可以在作为半导体衬底的剩余区域的外围电路区域上形成具有根据晶体管的功能而被优化以满足不同要求的结构的晶体管。 在该方法中，在单元阵列区域上形成单元晶体管。 单元晶体管包括陷波门结构，在陷波栅结构下形成在半导体衬底上的第一沟道区，形成在第一沟道区的两侧的源区和漏区，形成在第一沟道区之间的第一栅极绝缘膜 沟道区域和陷波门结构，以及局部地形成在与第一沟道区和陷波栅结构之间的源极和漏极区相邻的区域上的存储层。 在形成单元晶体管的同时，在外围电路区域上形成有包含至少一个具有与单元晶体管不同的结构的晶体管的多个外围电路晶体管。