公开(公告)号：US07338854B2

公开(公告)日：2008-03-04

申请号：US11002183

申请日：2004-12-03

申请人： Ho Sung Choo ,  Seung Hyun Ra ,  Yong Suk Kim ,  Jung Woo Lee ,  Hyo Soon Shin ,  Hyoung Ho Kim

发明人： Ho Sung Choo ,  Seung Hyun Ra ,  Yong Suk Kim ,  Jung Woo Lee ,  Hyo Soon Shin ,  Hyoung Ho Kim

IPC分类号： H01L21/8242

CPC分类号： H01G4/005 ,  H01G4/12 ,  H01G4/30 ,  Y10T29/417

摘要： A method for manufacturing a multilayer ceramic capacitor, in which internal electrodes printed on each of a plurality of dielectric sheets have reduced thicknesses using an absorption member, thereby allowing the multilayer ceramic capacitor to have a high capacity and be minimized. The method includes printing the internal electrodes on each of the dielectric sheets, and stacking the dielectric sheets, wherein the internal electrodes formed on each of the dielectric sheets have a reduced thickness by causing an absorptive member to contact the surface of each of the dielectric sheets provided with the internal electrodes and then separating the absorptive member from the surface so that portions of the internal electrodes having a designated thickness are eliminated, and the dielectric sheets provided with the internal electrodes having the reduced thickness are stacked to form a chip element.

摘要翻译： 一种制造多层陶瓷电容器的方法，其中印刷在多个电介质片材的每一个上的内部电极使用吸收构件具有减小的厚度，从而允许多层陶瓷电容器具有高容量并且被最小化。 该方法包括在每个电介质片上印刷内部电极，并叠放电介质片，其中形成在每个电介质片上的内部电极通过使吸收构件接触每个电介质片的表面而具有减小的厚度 设置有内部电极，然后将吸收构件从表面分离，使得部分具有指定厚度的内部电极被去除，并且设置有具有减小的厚度的内部电极的电介质层被堆叠以形成芯片元件。

公开(公告)号：US07203055B2

公开(公告)日：2007-04-10

申请号：US11011092

申请日：2004-12-15

申请人： Hyo Soon Shin ,  Seung Hyun Ra ,  Yong Suk Kim ,  Hyoung Ho Kim ,  Ho Sung Choo ,  Jung Woo Lee

发明人： Hyo Soon Shin ,  Seung Hyun Ra ,  Yong Suk Kim ,  Hyoung Ho Kim ,  Ho Sung Choo ,  Jung Woo Lee

IPC分类号： H01G4/228

CPC分类号： H01G4/30 ,  H01G4/1227 ,  Y10T29/417 ,  Y10T29/43 ,  Y10T29/435

摘要： Disclosed herein is a method of manufacturing a multilayered ceramic capacitor by a spin coating process, and a multilayered ceramic capacitor obtained by the above method. The method of the current invention provides a plurality of dielectric layers formed by spin coating, in which the process of coating the dielectric layer and the process of printing the inner electrode can be provided as a single process. Therefore, the thickness of the dielectric layer is easily controlled while the dielectric layer is formed to be thin. Further, since the dielectric layers and the inner electrodes are formed successively, the processes of separating and layering the dielectric layers, and the process of compressing the ceramic multilayered body can be omitted. Thereby, the ceramic multilayered body need not be compressed, and thus, a pillowing phenomenon does not occur in the multilayered ceramic capacitor.

摘要翻译： 本文公开了通过旋涂工艺制造多层陶瓷电容器的方法和通过上述方法获得的多层陶瓷电容器。 本发明的方法提供了通过旋涂形成的多个电介质层，其中涂覆介电层的过程和印刷内电极的过程可以作为单一工艺提供。 因此，在电介质层形成得较薄的同时容易控制电介质层的厚度。 此外，由于电介质层和内部电极依次形成，所以可以省略介电层的分离和分层工艺以及压缩陶瓷多层体的工艺。 因此，陶瓷多层体不需要被压缩，因此在多层陶瓷电容器中不会发生卷绕现象。

公开(公告)号：US07251119B2

公开(公告)日：2007-07-31

申请号：US11272893

申请日：2005-11-15

申请人： Hyoung Ho Kim ,  Hyo Soon Shin ,  Ho Sung Choo

发明人： Hyoung Ho Kim ,  Hyo Soon Shin ,  Ho Sung Choo

IPC分类号： H01G4/06 ,  H01G4/005

CPC分类号： H01G4/232 ,  H01G4/012 ,  Y10T29/413 ,  Y10T29/417 ,  Y10T29/435

摘要： A multilayer chip capacitor, and a method for manufacturing the same are provided. The capacitor includes a capacitor body having a plurality of dielectric layers stacked therein, a plurality of first and second internal electrodes formed on the dielectric layers, each of the internal electrodes including a main electrode portion and a lead portion, chip-protecting side members formed on both sides of the capacitor body to contact both sides of the first and second internal electrodes, and a pair of external electrodes formed on the outer surface of the capacitor body. The width of the main electrode portion is the same as that of the dielectric layers, and the width of the lead portion is smaller than that of the dielectric layers.

摘要翻译： 提供了一种多层片状电容器及其制造方法。 电容器包括：电容器体，其具有堆叠的多个电介质层;形成在电介质层上的多个第一和第二内部电极，每个内部电极包括主电极部分和引线部分，形成芯片保护侧部件 在电容器本体的两侧接触第一和第二内部电极的两侧，以及形成在电容器本体的外表面上的一对外部电极。 主电极部的宽度与电介质层的宽度相同，引线部的宽度小于电介质层的宽度。

公开(公告)号：US07644480B2

公开(公告)日：2010-01-12

申请号：US11822189

申请日：2007-07-03

申请人： Hyoung Ho Kim ,  Hyo Soon Shin ,  Ho Sung Choo

发明人： Hyoung Ho Kim ,  Hyo Soon Shin ,  Ho Sung Choo

IPC分类号： H01G4/005

CPC分类号： H01G4/232 ,  H01G4/012 ,  Y10T29/413 ,  Y10T29/417 ,  Y10T29/435

摘要： A method for manufacturing a multilayer chip capacitor includes: forming screen patterns on mother green sheets such that a widthwise margin is not formed on the mother green sheets, the screen patterns are spaced apart from each other in the width direction and the longitudinal direction, and a width of each screen pattern is greater than a spacing between the adjacent screen patterns; forming internal electrode patterns on the mother green sheets; forming a stack of the mother green sheets; forming a capacitor body having internal electrodes by cutting the stack of the mother green sheets along cutting lines arranged in the width direction and the longitudinal direction; forming chip-protecting side members on both sides of the capacitor body such that the chip-protecting side members contact both sides of the internal electrodes, respectively; and forming a pair of terminal electrodes on the outer surface of the capacitor body.

摘要翻译： 一种多层片式电容器的制造方法，其特征在于，在母版本上形成屏幕图案，使得母版未形成宽度方向的边缘，屏幕图案在宽度方向和长度方向上彼此间隔开， 每个屏幕图案的宽度大于相邻屏幕图案之间的间距; 在母板上形成内部电极图案; 形成一堆母亲的生页; 通过沿着宽度方向和长度方向布置的切割线切割母版本的叠层来形成具有内部电极的电容器体; 在电容器主体的两侧形成芯片保护侧部件，使得芯片保护侧部件分别接触内部电极的两侧; 以及在电容器主体的外表面上形成一对端子电极。

公开(公告)号：US20090214881A1

公开(公告)日：2009-08-27

申请号：US12388849

申请日：2009-02-19

申请人： Myung Whun Chang ,  Jong Myeon Lee ,  Soo Hyun Lyoo ,  Ho Sung Choo

发明人： Myung Whun Chang ,  Jong Myeon Lee ,  Soo Hyun Lyoo ,  Ho Sung Choo

IPC分类号： B32B18/00 ,  C03B29/00

CPC分类号： C04B37/005 ,  C04B2237/062 ,  C04B2237/10 ,  C04B2237/341 ,  C04B2237/62 ,  C04B2237/74 ,  H05K1/0306 ,  H05K1/162 ,  H05K3/4611 ,  H05K3/4629 ,  H05K3/4688

摘要： There is provided a low temperature co-fired ceramic substrate having a diffusion barrier layer to prevent diffusion occurring in a heterojunction during firing and a method of manufacturing the same. A low temperature co-fired ceramic substrate according to an aspect of the invention may include: a first ceramic layer formed of a material having a first dielectric constant; a second ceramic layer formed of a material having a second dielectric constant lower than the first dielectric constant; and a diffusion barrier layer interposed between the first ceramic layer and the second ceramic layer and formed of the first ceramic layer material, the second ceramic layer material, and a barium (Ba) compound, wherein inter-diffusion between the first ceramic layer material and the second ceramic layer material is prevented by using the diffusion barrier layer.

摘要翻译： 提供了具有扩散阻挡层的低温共烧陶瓷基板及其制造方法，以防止在烧成期间发生异质结的扩散。 根据本发明的一个方面的低温共烧陶瓷衬底可以包括：由具有第一介电常数的材料形成的第一陶瓷层; 由具有低于第一介电常数的第二介电常数的材料形成的第二陶瓷层; 以及介于所述第一陶瓷层和所述第二陶瓷层之间并且由所述第一陶瓷层材料，所述第二陶瓷层材料和钡（Ba）化合物形成的扩散阻挡层，其中所述第一陶瓷层材料和 通过使用扩散阻挡层来防止第二陶瓷层材料。

公开(公告)号：US08557617B2

公开(公告)日：2013-10-15

申请号：US11709130

申请日：2007-02-22

申请人： Youn Gon Park ,  Jong Myeon Lee ,  Hai Sung Lee ,  Myung Whun Chang ,  Ho Sung Choo

发明人： Youn Gon Park ,  Jong Myeon Lee ,  Hai Sung Lee ,  Myung Whun Chang ,  Ho Sung Choo

IPC分类号： H01L21/00

CPC分类号： H01L33/54 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2924/00014

摘要： A method of manufacturing a light emitting diode package. A cup-shaped package structure with a recess formed therein and an electrode structure formed on a bottom of the recess is prepared. A light emitting diode chip is mounted on a bottom of the recess with a terminal of the chip electrically connected to the electrode structure. A liquid-state transparent resin is injected in the recess and before the liquid-state transparent resin is completely cured, a stamp with a micro rough pattern engraved thereon is applied on an upper surface of the resin. The liquid-state transparent resin is cured with the stamp applied thereon to form a resin encapsulant and the stamp is removed from the resin encapsulant.

摘要翻译： 一种制造发光二极管封装的方法。 制备其中形成有凹部的杯形封装结构和形成在凹部的底部上的电极结构。 发光二极管芯片安装在凹部的底部，其中芯片的端子电连接到电极结构。 将液态透明树脂注入到凹部中，并且在液态透明树脂完全固化之前，将刻有其上的微粗糙图案的印模涂布在树脂的上表面上。 液态透明树脂用施加在其上的印模固化以形成树脂密封剂，并且从树脂密封剂中除去印模。

公开(公告)号：US20120199270A1

公开(公告)日：2012-08-09

申请号：US13448259

申请日：2012-04-16

申请人： Beom Joon Cho ,  Jong Myeon Lee ,  Ho Sung Choo

发明人： Beom Joon Cho ,  Jong Myeon Lee ,  Ho Sung Choo

IPC分类号： B32B37/06 ,  B32B38/10

CPC分类号： H05K3/4611 ,  H05K1/0306 ,  H05K3/4629 ,  H05K2201/0266 ,  H05K2203/308 ,  Y10T428/24992

摘要： Provided are a method of manufacturing a multi-layer ceramic substrate. The method includes preparing a non-sintered ceramic laminated structure formed of a plurality of ceramic green sheets; preparing one or more constraining green sheets comprising a first constraining layer formed of a first inorganic powder having a first particle diameter and a second constraining layer formed of a second inorganic powder having a second particle diameter larger than the first particle diameter; disposing the constraining green sheets on the top and the bottom of the ceramic laminated structure; and firing the ceramic laminated structure at a predetermined firing temperature.

摘要翻译： 提供一种制造多层陶瓷基板的方法。 该方法包括制备由多个陶瓷生片形成的非烧结陶瓷层压结构; 制备一个或多个约束生片，其包括由具有第一粒径的第一无机粉末和由具有大于第一粒径的第二粒径的第二无机粉末形成的第二约束层形成的第一约束层; 将约束生片设置在陶瓷层叠结构的顶部和底部; 并在预定的烧制温度下烧制陶瓷层叠结构。

公开(公告)号：US07842333B2

公开(公告)日：2010-11-30

申请号：US11524952

申请日：2006-09-22

申请人： Hai Sung Lee ,  Jong Myeon Lee ,  Ho Sung Choo ,  Myung Whun Chang ,  Youn Gon Park

发明人： Hai Sung Lee ,  Jong Myeon Lee ,  Ho Sung Choo ,  Myung Whun Chang ,  Youn Gon Park

IPC分类号： B05D5/06 ,  B05D1/12 ,  B05D7/00

CPC分类号： C09K11/7749 ,  C09K11/025 ,  H01L33/502 ,  H01L2933/0041

摘要： The invention relates to a method of forming a phosphor film and a method of manufacturing an LED package incorporating the same. The method of forming a phosphor film includes mixing phosphor and light-transmitting beads in an aqueous solvent such that the nano-sized light-transmitting beads having a first charge are adsorbed onto surfaces of phosphor particles having a second charge. The method also includes coating a phosphor mixture obtained from the mixing step on an area where the phosphor film is to be formed, and drying the coated phosphor mixture to form the phosphor film. The invention further provides a method of manufacturing an LED package incorporating the method of forming the phosphor film.

摘要翻译： 本发明涉及一种形成荧光膜的方法及其制造方法。 形成荧光体膜的方法包括在水性溶剂中混合荧光体和透光珠，使得具有第一电荷的纳米尺寸的透光珠吸附在具有第二电荷的荧光体颗粒的表面上。 该方法还包括将从混合步骤获得的荧光体混合物涂覆在要形成荧光膜的区域上，并干燥涂覆的荧光体混合物以形成荧光膜。 本发明还提供一种制造包含形成荧光膜的方法的LED封装的方法。

公开(公告)号：US08178193B2

公开(公告)日：2012-05-15

申请号：US12260042

申请日：2008-10-28

申请人： Beom Joon Cho ,  Jong Myeon Lee ,  Ho Sung Choo

发明人： Beom Joon Cho ,  Jong Myeon Lee ,  Ho Sung Choo

IPC分类号： B32B7/02 ,  B32B37/06 ,  B32B9/04

CPC分类号： H05K3/4611 ,  H05K1/0306 ,  H05K3/4629 ,  H05K2201/0266 ,  H05K2203/308 ,  Y10T428/24992

摘要： Provided are a constraining green sheet and a method of manufacturing a multi-layer ceramic substrate. The constraining green sheet includes a first constraining layer and a second constraining layer. The first constraining layer has a side to be disposed on a multi-layer ceramic laminated structure and is formed of a first inorganic powder having a first particle diameter. The second constraining layer is disposed on top of the first constraining layer and is formed of a second inorganic powder having a second particle diameter larger than the first particle diameter. The second constraining layer is equal to or lower than the first constraining layer in terms of powder packing density. A shrinkage suppression rate can be increased and a de-binder passage can be secured in a firing process of the ceramic laminated structure by using the constraining green sheet formed of inorganic powders having different density and particle diameter.

摘要翻译： 本发明提供约束生片和多层陶瓷基片的制造方法。 约束生片包括第一约束层和第二约束层。 第一约束层具有设置在多层陶瓷层叠结构上的一侧，并且由具有第一粒径的第一无机粉末形成。 第二约束层设置在第一约束层的顶部，并且由具有大于第一粒径的第二粒径的第二无机粉末形成。 关于粉末填充密度，第二约束层等于或低于第一约束层。 通过使用由具有不同密度和粒径的无机粉末形成的约束生片，可以在陶瓷层压结构的烧制过程中确保收缩抑制率，并且可以确保去粘合剂通道。

公开(公告)号：US08093172B2

公开(公告)日：2012-01-10

申请号：US12271386

申请日：2008-11-14

申请人： Ho Sung Choo ,  Jong Myeon Lee ,  Eun Tae Park ,  Myung Whun Chang ,  Soo Hyun Lyoo ,  Beom Joon Cho

发明人： Ho Sung Choo ,  Jong Myeon Lee ,  Eun Tae Park ,  Myung Whun Chang ,  Soo Hyun Lyoo ,  Beom Joon Cho

IPC分类号： C04B35/468

CPC分类号： H01G4/1227 ,  C03C3/064 ,  C03C8/02 ,  C04B35/4682 ,  C04B2235/3215 ,  C04B2235/3232 ,  C04B2235/3298 ,  C04B2235/3409 ,  C04B2235/3418 ,  C04B2235/36 ,  C04B2235/5445 ,  H01G4/129 ,  H05K1/0306 ,  H05K1/162 ,  H05K3/4611 ,  H05K3/4629 ,  H05K3/4688

摘要： Provided are a glass composition, a dielectric composition and a multi-layer ceramic capacitor embedded low temperature co-fired ceramic substrate using the same. The multi-layer ceramic capacitor embedded low temperature co-fired ceramic substrate is sinterable at a low temperature while showing a high dielectric constant. The glass composition includes a composition component expressed by a composition formula of aBi2O3-bB2O3-cSiO2-dBaO-eTiO2, where a+b+c+d+e=100, and a, b, c, d, and e are 40≦a≦89, 10≦b≦50, 1≦c≦20, 0≦d≦10, and 0≦e≦10, respectively.

摘要翻译： 提供一种玻璃组合物，电介质组合物和使用其的多层陶瓷电容器嵌入式低温共烧陶瓷基板。 多层陶瓷电容器嵌入式低温共烧陶瓷基板在低温下可烧结，同时显示高介电常数。 该玻璃组合物包含由Bi 2 O 3 -bB 2 O 3 -cSiO 2 -dBaO-eTiO 2的组成式表示的组成成分，其中a + b + c + d + e = 100，a，b，c，d和e为40＆ a＆nlE; 89，10＆nlE; b＆nlE; 50,1＆nlE; c＆nlE; 20,0＆nlE; d＆nlE; 10和0＆nlE; e＆nlE; 10。