公开(公告)号：US20130099240A1

公开(公告)日：2013-04-25

申请号：US13650528

申请日：2012-10-12

申请人： Hyun-Jung LEE ,  Sung-Haeng CHO ,  Woo-Geun LEE ,  Jang-Hoon HA ,  Hee-Jun BYEON ,  Ji-Yun HONG ,  Ji-Soo OH

发明人： Hyun-Jung LEE ,  Sung-Haeng CHO ,  Woo-Geun LEE ,  Jang-Hoon HA ,  Hee-Jun BYEON ,  Ji-Yun HONG ,  Ji-Soo OH

IPC分类号： H01L29/786 ,  H01L21/34

CPC分类号： H01L29/78693 ,  H01L27/1225 ,  H01L29/41733 ,  H01L29/78606 ,  H01L29/7869

摘要： A Thin Film Transistor (TFT) includes a substrate, a semiconductor layer disposed on the substrate a first source electrode and a first drain electrode spaced apart from each other on the semiconductor layer, a channel area disposed in the semiconductor layer between the first source electrode and the first drain electrode, an etching prevention layer disposed on the channel area, the first source electrode, and the first drain electrode and a second source electrode in contact with the first source electrode, and a second drain electrode in contact with the first drain electrode.

公开(公告)号：US20120217493A1

公开(公告)日：2012-08-30

申请号：US13365704

申请日：2012-02-03

申请人： Jin-Won LEE ,  Woo Geun LEE ,  Kap Soo YOON ,  Ki-Won KIM ,  Hyun-Jung LEE ,  Hee-Jun BYEON ,  Ji-Soo OH

发明人： Jin-Won LEE ,  Woo Geun LEE ,  Kap Soo YOON ,  Ki-Won KIM ,  Hyun-Jung LEE ,  Hee-Jun BYEON ,  Ji-Soo OH

IPC分类号： H01L29/786 ,  H01L33/02 ,  H01L29/24

CPC分类号： H01L27/1225 ,  H01L29/41733

摘要： A thin film transistor array panel includes: a gate electrode disposed on an insulation substrate; a gate insulating layer disposed on the gate electrode; a first electrode and an oxide semiconductor disposed directly on the gate insulating layer; a source electrode and a drain electrode formed on the oxide semiconductor; a passivation layer disposed on the first electrode, the source electrode, and the drain electrode; and a second electrode disposed on the passivation layer.

摘要翻译： 薄膜晶体管阵列面板包括：设置在绝缘基板上的栅电极; 设置在栅电极上的栅极绝缘层; 直接设置在栅极绝缘层上的第一电极和氧化物半导体; 形成在所述氧化物半导体上的源电极和漏电极; 设置在所述第一电极，所述源电极和所述漏电极上的钝化层; 以及设置在钝化层上的第二电极。

公开(公告)号：US20110272696A1

公开(公告)日：2011-11-10

申请号：US13092882

申请日：2011-04-22

申请人： Hye-Young RYU ,  Jin-Won LEE ,  Woo-Geun LEE ,  Hee-Jun BYEON ,  Xun ZHU

发明人： Hye-Young RYU ,  Jin-Won LEE ,  Woo-Geun LEE ,  Hee-Jun BYEON ,  Xun ZHU

IPC分类号： H01L29/786 ,  H01L33/08 ,  H01L21/44

CPC分类号： H01L27/1288 ,  H01L27/1214 ,  H01L27/1225 ,  H01L27/1248 ,  H01L27/3272 ,  H01L51/5253 ,  H01L2227/323

摘要： A thin film transistor panel includes a substrate, a light blocking layer on the substrate, a first protective film on the light blocking layer, a first electrode and a second electrode on the first protective film, an oxide semiconductor layer on a portion of the first protective film exposed between the first electrode and the second electrode, an insulating layer, a third electrode overlapping with the oxide semiconductor layer and on the insulating layer, and a fourth electrode on the insulating layer. The light blocking layer includes first sidewalls, and the first protective film includes second sidewalls. The first and the second sidewalls are disposed along substantially the same line.

摘要翻译： 薄膜晶体管面板包括基板，基板上的阻光层，遮光层上的第一保护膜，第一保护膜上的第一电极和第二电极，第一保护膜的一部分上的氧化物半导体层 在第一电极和第二电极之间暴露的保护膜，绝缘层，与氧化物半导体层重叠的绝缘层和绝缘层上的第四电极。 遮光层包括第一侧壁，并且第一保护膜包括第二侧壁。 第一和第二侧壁沿着基本相同的线设置。

公开(公告)号：US20120037906A1

公开(公告)日：2012-02-16

申请号：US13115088

申请日：2011-05-24

申请人： Hye-Young RYU ,  Woo-Geun LEE ,  Young-Joo CHOI ,  Kyoung-Jae CHUNG ,  Jin-Won LEE ,  Seung-Ha CHOI ,  Hee-Jun BYEON ,  Pil-Sang YUN

发明人： Hye-Young RYU ,  Woo-Geun LEE ,  Young-Joo CHOI ,  Kyoung-Jae CHUNG ,  Jin-Won LEE ,  Seung-Ha CHOI ,  Hee-Jun BYEON ,  Pil-Sang YUN

IPC分类号： H01L29/786 ,  H01L21/44

CPC分类号： H01L27/1214 ,  H01L27/1225 ,  H01L27/1255

摘要： A thin film transistor array substrate capable of reducing degradation of a device due to degradation of an oxide semiconductor pattern and a method of fabricating the same are provided. The thin film transistor array substrate may include an insulating substrate on which a gate electrode is formed, a gate insulating film formed on the insulating substrate, an oxide semiconductor pattern disposed on the gate insulating film, an anti-etching pattern formed on the oxide semiconductor pattern, and a source electrode and a drain electrode formed on the anti-etching pattern. The oxide semiconductor pattern may include an edge portion positioned between the source electrode and the drain electrode, and the edge portion may include at least one conductive region and at least one non-conductive region.

摘要翻译： 提供了能够降低由于氧化物半导体图案的劣化引起的器件劣化的薄膜晶体管阵列基板及其制造方法。 薄膜晶体管阵列基板可以包括其上形成有栅极的绝缘基板，形成在绝缘基板上的栅极绝缘膜，设置在栅极绝缘膜上的氧化物半导体图案，形成在氧化物半导体上的抗蚀刻图案 图案，以及形成在防蚀刻图案上的源电极和漏电极。 氧化物半导体图案可以包括位于源电极和漏电极之间的边缘部分，并且边缘部分可以包括至少一个导电区域和至少一个非导电区域。