公开(公告)号：US5956279A

公开(公告)日：1999-09-21

申请号：US19519

申请日：1998-02-05

申请人： Hyun-Sun Mo ,  Choong-Keun Kwak

发明人： Hyun-Sun Mo ,  Choong-Keun Kwak

IPC分类号： G11C11/413 ,  G11C29/34 ,  G11C7/00

CPC分类号： G11C29/34

摘要： A static random access memory (SRAM) device comprises an array of memory cells, a plurality of bit line precharge circuit for selectively delivering current to bit lines in response to a pair of control signals, during normal and burn-in test modes, and a burn-in current source circuit for selectively delivering current to the memory cells selected by the word lines along with the precharge circuit, in response to the control signals, during the burn-in test mode. In burn-in write operation, memory cells can be supplied with enough cell current without large increasing of chip size and power consumption in normal operation mode.

摘要翻译： 静态随机存取存储器（SRAM）装置包括存储器单元阵列，多个位线预充电电路，用于在正常和老化测试模式期间响应于一对控制信号选择性地将电流输送到位线;以及 老化电流源电路，用于在老化测试模式期间响应于控制信号选择性地将电流与预充电电路一起输送到由字线选择的存储器单元。 在老化写入操作中，在正常操作模式下，存储单元可以提供足够的单元电流，而不会大大增加芯片尺寸和功耗。

公开(公告)号：US06456547B1

公开(公告)日：2002-09-24

申请号：US09689098

申请日：2000-10-12

申请人： Hyun-Sun Mo ,  Du-Eung Kim ,  Choong-Keun Kwak

发明人： Hyun-Sun Mo ,  Du-Eung Kim ,  Choong-Keun Kwak

IPC分类号： G11C700

CPC分类号： G11C29/83 ,  G11C7/12

摘要： A semiconductor memory device having memory cells connected with pairs of bit lines and word lines comprises a pre-charging part for pre-charging a pair of bit lines in response to a first state control signal at a stand-by mode of the semiconductor memory device; a bit line charging control part for generating a second state control signal to the pre-charging part when a stand-by current failure occurs due to defect in the pair of bit lines, wherein the second state control signal is independent of a pre-charge relating signal externally applied and the pre-charging part cuts-off a supply voltage from being applied to the pair of bit lines with defect; and a bit line floating prevent part for compensatively fixing potential values of the pair of bit lines with defect so that a cell supply voltage is prevented from being applied to the pair of bit lines with defect at a memory access mode of the semiconductor memory device, so that a hard type defect like a stand-by current failure can be repaired regardless of a logic state of a pre-charge control signal, thereby reducing the probability of occurrence of defect in a semiconductor memory device.

摘要翻译： 具有与位线对和字线对连接的存储单元的半导体存储器件包括预充电部分，用于响应于半导体存储器件的待机模式下的第一状态控制信号对一对位线进行预充电 ; 位线充电控制部分，用于当由于一对位线中的缺陷而发生待机电流故障时，向预充电部分产生第二状态控制信号，其中第二状态控制信号独立于预充电 相关信号外部施加，并且预充电部分切断电源电压而不被施加到一对位线; 以及位线浮动防止部件，用于以缺陷补偿地固定一对位线的电位值，使得防止单元电源电压被施加到半导体存储器件的存储器访问模式下的缺陷的位线对， 使得像预备电流故障那样的硬型缺陷可以被修复，而不管预充电控制信号的逻辑状态如何，从而降低了半导体存储器件中的缺陷的发生概率。

公开(公告)号：US07796425B2

公开(公告)日：2010-09-14

申请号：US11985975

申请日：2007-11-19

申请人： Byung-Gil Choi ,  Choong-Keun Kwak ,  Woo-Yeong Cho

发明人： Byung-Gil Choi ,  Choong-Keun Kwak ,  Woo-Yeong Cho

IPC分类号： G11C11/00 ,  G11C7/04 ,  G11C11/4193 ,  G11C11/4197

CPC分类号： G11C13/0069 ,  G11C7/04 ,  G11C7/1078 ,  G11C7/1096 ,  G11C13/0004 ,  G11C2013/0078

摘要： A driver circuit for a PRAM (phase-change random access memory) device includes a write driver that generates a set/reset current in response to a set/reset pulse. In addition, a temperature compensator controls a pulse width of the set/reset pulse in response to a peripheral temperature of the PRAM device. For example, the temperature compensator maintains the pulse width to be substantially constant irrespective of the peripheral temperature. In another example, the temperature compensator decreases the pulse width for higher peripheral temperature.

摘要翻译： 用于PRAM（相变随机存取存储器）装置的驱动器电路包括响应于置位/复位脉冲而产生置位/复位电流的写入驱动器。 此外，温度补偿器响应于PRAM器件的外围温度来控制置位/复位脉冲的脉冲宽度。 例如，温度补偿器将脉冲宽度保持为基本恒定，而与外围温度无关。 在另一个例子中，温度补偿器降低脉冲宽度，以提高外围温度。

公开(公告)号：US20080212362A1

公开(公告)日：2008-09-04

申请号：US11985975

申请日：2007-11-19

申请人： Byung-Gil Choi ,  Choong-Keun Kwak ,  Woo-Yeong Cho

发明人： Byung-Gil Choi ,  Choong-Keun Kwak ,  Woo-Yeong Cho

IPC分类号： G11C11/00 ,  G11C7/00

CPC分类号： G11C13/0069 ,  G11C7/04 ,  G11C7/1078 ,  G11C7/1096 ,  G11C13/0004 ,  G11C2013/0078

摘要： A driver circuit for a PRAM (phase-change random access memory) device includes a write driver that generates a set/reset current in response to a set/reset pulse. In addition, a temperature compensator controls a pulse width of the set/reset pulse in response to a peripheral temperature of the PRAM device. For example, the temperature compensator maintains the pulse width to be substantially constant irrespective of the peripheral temperature. In another example, the temperature compensator decreases the pulse width for higher peripheral temperature.

摘要翻译： 用于PRAM（相变随机存取存储器）装置的驱动器电路包括响应于置位/复位脉冲而产生置位/复位电流的写入驱动器。 此外，温度补偿器响应于PRAM器件的外围温度来控制置位/复位脉冲的脉冲宽度。 例如，温度补偿器将脉冲宽度保持为基本恒定，而与外围温度无关。 在另一个例子中，温度补偿器降低脉冲宽度，以提高外围温度。

公开(公告)号：US07315469B2

公开(公告)日：2008-01-01

申请号：US11124341

申请日：2005-05-06

申请人： Byung-Gil Choi ,  Choong-Keun Kwak ,  Woo-Yeong Cho

发明人： Byung-Gil Choi ,  Choong-Keun Kwak ,  Woo-Yeong Cho

IPC分类号： G11C11/00 ,  G11C7/04 ,  G11C7/22

CPC分类号： G11C13/0069 ,  G11C7/04 ,  G11C7/1078 ,  G11C7/1096 ,  G11C13/0004 ,  G11C2013/0078

摘要： A drive circuit for a PRAM (phase-change random access memory) device includes a write driver that generates a set/reset current in response to a set/reset pulse. In addition, a temperature compensator controls a pulse width of the set/reset pulse in response to a peripheral temperature of the PRAM device. For example, the temperature compensator maintains the pulse width to be substantially constant irrespective of the peripheral temperature. In another example, the temperature compensator decreases the width for higher peripheral temperature.

摘要翻译： 用于PRAM（相变随机存取存储器）装置的驱动电路包括响应于置位/复位脉冲而产生置位/复位电流的写入驱动器。 此外，温度补偿器响应于PRAM器件的外围温度来控制置位/复位脉冲的脉冲宽度。 例如，温度补偿器将脉冲宽度保持为基本恒定，而与外围温度无关。 在另一个例子中，温度补偿器减小了较高外围温度的宽度。

公开(公告)号：US20060274574A1

公开(公告)日：2006-12-07

申请号：US11502563

申请日：2006-08-11

申请人： Byung-Gil Choi ,  Choong-Keun Kwak ,  Du-Eung Kim ,  Beak-Hyung Cho

发明人： Byung-Gil Choi ,  Choong-Keun Kwak ,  Du-Eung Kim ,  Beak-Hyung Cho

IPC分类号： G11C11/00

CPC分类号： G11C13/0069 ,  G11C13/0004 ,  G11C13/0023 ,  G11C2013/0078 ,  G11C2013/0092

摘要： A phase-change cell memory device includes a plurality of phase-change memory cells, an address circuit, a write driver, and a write driver control circuit. The phase-change memory cells each include a volume of material that is programmable between amorphous and crystalline states. The address circuit selects at least one of the memory cells, and the write driver generates a reset pulse current to program a memory cell selected by the address circuit into the amorphous state, and a set pulse current to program the memory cell selected by the address circuit into the crystalline state. The write driver control circuit varies at least one of a pulse width and a pulse count of at least one of the reset and set pulse currents according to a load between the write driver and the memory cell selected by the address circuit.

公开(公告)号：US07064601B2

公开(公告)日：2006-06-20

申请号：US09955458

申请日：2001-09-18

申请人： Choong-Keun Kwak ,  Du-Eung Kim ,  Woo-Yeong Cho

发明人： Choong-Keun Kwak ,  Du-Eung Kim ,  Woo-Yeong Cho

IPC分类号： G05F1/46

CPC分类号： G05F3/262

摘要： A reference voltage generating circuit includes a current mirror circuit having first and second current paths formed between a first power source terminal and a second power source terminal in which the current mirror circuit is operated in response to a voltage level of the second current path, a reference voltage output node for providing a reference voltage and being located on the second current path, an active resistance device formed on the first current path to be operated in a linear region of a current-voltage characteristic curve of the active resistance device, and a voltage supply circuit for supplying the active resistance device with an enable voltage to control the active resistance device to be operated in the linear region.

公开(公告)号：US20060050548A1

公开(公告)日：2006-03-09

申请号：US11220294

申请日：2005-09-06

申请人： Hyung-Rok Oh ,  Baek-Hyung Cho ,  Choong-Keun Kwak

发明人： Hyung-Rok Oh ,  Baek-Hyung Cho ,  Choong-Keun Kwak

IPC分类号： G11C11/00

CPC分类号： G11C7/12 ,  G11C7/14 ,  G11C13/0004 ,  G11C13/0026 ,  G11C13/004 ,  G11C2013/0054 ,  G11C2213/79

摘要： A semiconductor memory device compensates leakage current. A plurality of memory cells is disposed at intersections of word lines and bit lines. A plurality of dummy cells is connected to at least one dummy bit line. A leakage compensation circuit is connected to the at least one dummy bit line that outputs a leakage compensation current to at least one of the bit lines. A read current supply circuit outputs a read current necessary for a read operation to at least one of the bit lines in response to a first control signal. The memory device is a phase-change memory device containing phase-change material. The semiconductor memory device compensates leakage current in a read operation and supplies the leakage compensation current to a selected bit line, thereby suppressing error operation occurrence caused by leakage current.

摘要翻译： 半导体存储器件补偿漏电流。 多个存储单元设置在字线和位线的交点处。 多个虚拟单元被连接到至少一个虚拟位线。 泄漏补偿电路连接到至少一个虚拟位线，其向至少一个位线输出泄漏补偿电流。 读取电流供应电路响应于第一控制信号向至少一个位线输出读取操作所需的读取电流。 存储器件是包含相变材料的相变存储器件。 半导体存储器件在读取操作中补偿漏电流，并将泄漏补偿电流提供给所选择的位线，从而抑制由漏电流引起的误操作发生。

公开(公告)号：US20050281106A1

公开(公告)日：2005-12-22

申请号：US11146513

申请日：2005-06-07

申请人： Gong-Heum Han ,  Choong-Keun Kwak ,  Joon-Min Park

发明人： Gong-Heum Han ,  Choong-Keun Kwak ,  Joon-Min Park

IPC分类号： G11C5/14 ,  G11C7/00 ,  G11C11/417

CPC分类号： G11C11/417 ,  G11C5/147

摘要： A semiconductor memory device, which has an array of memory cells connected with a plurality of bit line pairs and a plurality of word lines, to perform a read or write operation of data, having low power consumption is provided. The device includes a first power supply for supplying a first power source voltage. Also, a second power supply supplies a second power source voltage having a lower voltage level than the first power source voltage. Further, the device includes a standard ground. An elevated ground circuit provides an elevated ground voltage having a higher voltage level than that of the standard ground. A first power circuit is connected with the first power supply and the standard ground, and operates in response to the first power source voltage. A second power circuit is connected with the second power supply and the elevated ground circuit, and operates in response to the second power source voltage. Thereby, power and chip size can be reduced.

摘要翻译： 提供具有与多个位线对和多个字线连接的存储单元的阵列以执行具有低功耗的数据的读取或写入操作的半导体存储器件。 该装置包括用于提供第一电源电压的第一电源。 此外，第二电源提供具有比第一电源电压低的电压电平的第二电源电压。 此外，该装置包括标准接地。 提升的接地电路提供比标准接地电压高的电压电平的升高的接地电压。 第一电源电路与第一电源和标准接地相连接，并响应于第一电源电压而工作。 第二电源电路与第二电源和升高的接地电路连接，并且响应于第二电源电压而工作。 从而可以降低功率和芯片尺寸。

公开(公告)号：US06657264B2

公开(公告)日：2003-12-02

申请号：US09940733

申请日：2001-08-28

申请人： Beak-Hyung Cho ,  Choong-Keun Kwak

发明人： Beak-Hyung Cho ,  Choong-Keun Kwak

IPC分类号： H01L2994

CPC分类号： H01L27/0921 ,  H01L27/0266

摘要： A layout method is provided for a latch-up prevention circuit of a semiconductor memory device which includes the steps of: arranging a cell array at substantially the middle of the device; placing peripheral circuits next to both sides of the cell array; placing a plurality of pads on both sides of the cell array between the peripheral circuits and both edges of the device; and arranging guard rings beneath the plurality of pads. The layout method further includes a plurality of ESD protection transistors disposed axially along the direction as the plurality of pads between the plurality of pads and an edge of the device. And each of guard ring is a NWELL guard ring, and connected to a supply voltage and ground.