公开(公告)号：US20070123040A1

公开(公告)日：2007-05-31

申请号：US11418720

申请日：2006-05-05

Applicant: Chang-Youn Hwang ,  Hyung-Hwan Kim ,  Ik-Soo Choi ,  Hae-Jung Lee

Inventor： Chang-Youn Hwang ,  Hyung-Hwan Kim ,  Ik-Soo Choi ,  Hae-Jung Lee

IPC: H01L21/44

CPC classification number: H01L21/76897 ,  H01L21/76804 ,  H01L21/76831 ,  H01L27/10855

Abstract: A method for forming a storage node contact plug in a semiconductor device is provided. The method includes: forming an inter-layer insulation layer over a substrate having a conductive plug; etching a portion of the inter-layer insulation layer using at least line type storage node contact masks as an etch mask to form a first contact hole with sloping sidewalls; etching another portion of the inter-layer insulation layer underneath the first contact hole to form a second contact hole exposing the conductive plug, the second contact hole having substantially vertical sidewalls; and filling the first and second storage node contact holes to form a storage node contact plug.

Abstract translation: 提供一种在半导体器件中形成存储节点接触插头的方法。 该方法包括：在具有导电插塞的基板上形成层间绝缘层; 使用至少线型存储节点接触掩模作为蚀刻掩模蚀刻层间绝缘层的一部分，以形成具有倾斜侧壁的第一接触孔; 蚀刻在第一接触孔下面的层间绝缘层的另一部分，以形成露出导电插塞的第二接触孔，第二接触孔具有基本垂直的侧壁; 以及填充所述第一和第二存储节点接触孔以形成存储节点接触插头。

公开(公告)号：US08786047B2

公开(公告)日：2014-07-22

申请号：US13544411

申请日：2012-07-09

Applicant: Hyung-Hwan Kim ,  Bong-Ho Choi ,  Jin-Yul Lee ,  Seung-Seok Pyo

Inventor： Hyung-Hwan Kim ,  Bong-Ho Choi ,  Jin-Yul Lee ,  Seung-Seok Pyo

IPC: H01L21/70 ,  H01L21/762

CPC classification number: H01L21/76224 ,  H01L21/762 ,  H01L21/76229 ,  H01L27/10894

Abstract: A semiconductor device with an isolation layer buried in a trench includes an interface layer formed on the surface of the trench, a buffer layer formed in the interface layer at a bottom corner of the trench, a liner layer formed over the interface layer, and a gap-fill layer gap-filling the trench over the liner layer. The trench includes a micro-trench formed at the bottom corner thereof, and the buffer layer fills the micro-trench.

Abstract translation: 埋置在沟槽中的具有隔离层的半导体器件包括形成在沟槽表面上的界面层，形成在沟槽底部拐角处的界面层中的缓冲层，形成在界面层上的衬层，以及 间隙填充层间隙填充衬里层上的沟槽。 沟槽包括形成在其底角处的微沟槽，并且缓冲层填充微沟槽。

公开(公告)号：US20050142824A1

公开(公告)日：2005-06-30

申请号：US10876590

申请日：2004-06-28

Applicant: Hyung-Hwan Kim

Inventor： Hyung-Hwan Kim

IPC: H01L21/283 ,  H01L21/02 ,  H01L21/28 ,  H01L21/30 ,  H01L21/4763 ,  H01L21/60 ,  H01L21/768 ,  H01L21/822

CPC classification number: H01L21/76897

Abstract: Disclosed is a method for forming landing plug contacts in a semiconductor device. The method includes the steps of: forming a plurality of gate structures on a substrate, each gate structure including a gate hard mask; forming an inter-layer insulation layer on the gate structures; planarizing the inter-layer insulation layer through a chemical mechanical polishing (CMP) process until the gate hard mask is exposed; forming a hard mask material on the planarized inter-layer insulation layer; patterning the hard mask material, thereby forming a hard mask; forming a plurality of contact holes exposing the substrate disposed between the gate structures by etching the planarized inter-layer insulation layer with use of the hard mask as an etch mask; forming a polysilicon layer on the contact holes; and forming the landing plug contacts buried into the contact holes through a planarization process performed to the polysilicon layer until the gate hard mask is exposed.

Abstract translation: 公开了一种在半导体器件中形成着地插头触点的方法。 该方法包括以下步骤：在衬底上形成多个栅极结构，每个栅极结构包括栅极硬掩模; 在栅极结构上形成层间绝缘层; 通过化学机械抛光（CMP）工艺对层间绝缘层进行平坦化，直到栅极硬掩模露出; 在平坦化的层间绝缘层上形成硬掩模材料; 图案化硬掩模材料，由此形成硬掩模; 通过使用硬掩模作为蚀刻掩模蚀刻平坦化的层间绝缘层，形成暴露通过栅极结构之间设置的衬底的多个接触孔; 在所述接触孔上形成多晶硅层; 以及通过对所述多晶硅层进行的平坦化处理形成所述着陆栓接触件，所述接地孔接触件埋入所述接触孔中，直到所述栅极硬掩模露出为止。

公开(公告)号：US08384188B2

公开(公告)日：2013-02-26

申请号：US13470843

申请日：2012-05-14

Applicant: Hyung-Hwan Kim

Inventor： Hyung-Hwan Kim

IPC: H01L21/70

CPC classification number: H01L21/76229 ,  H01L27/11546

Abstract: A method for fabricating a semiconductor device includes: providing a substrate; forming a plurality of trenches by etching the substrate; forming a first isolation layer by filling the plurality of the trenches with a first insulation layer; recessing the first insulation layer filling a first group of the plurality of the trenches to a predetermined depth; forming a liner layer over the first group of the trenches with the first insulation layer recessed to the predetermined depth; and forming a second isolation layer by filling the first group of the trenches, where the liner layer is formed, with a second insulation layer.

Abstract translation: 一种制造半导体器件的方法包括：提供衬底; 通过蚀刻所述衬底形成多个沟槽; 通过用第一绝缘层填充多个沟槽来形成第一隔离层; 使第一绝缘层将所述多个沟槽中的第一组填充到预定深度; 在所述第一组沟槽上形成衬里层，其中所述第一绝缘层凹入所述预定深度; 以及通过用形成有衬垫层的第一组沟槽填充第二绝缘层来形成第二隔离层。

公开(公告)号：US20110101488A1

公开(公告)日：2011-05-05

申请号：US12640118

申请日：2009-12-17

Applicant: Hyung-Hwan Kim

Inventor： Hyung-Hwan Kim

IPC: H01L29/06 ,  H01L21/762

CPC classification number: H01L21/76229 ,  H01L27/11546

Abstract: A method for fabricating a semiconductor device includes: providing a substrate; forming a plurality of trenches by etching the substrate; forming a first isolation layer by filling the plurality of the trenches with a first insulation layer; recessing the first insulation layer filling a first group of the plurality of the trenches to a predetermined depth; forming a liner layer over the first group of the trenches with the first insulation layer recessed to the predetermined depth; and forming a second isolation layer by filling the first group of the trenches, where the liner layer is formed, with a second insulation layer.

Abstract translation: 一种制造半导体器件的方法包括：提供衬底; 通过蚀刻所述衬底形成多个沟槽; 通过用第一绝缘层填充多个沟槽来形成第一隔离层; 使第一绝缘层将所述多个沟槽中的第一组填充到预定深度; 在所述第一组沟槽上形成衬里层，其中所述第一绝缘层凹入所述预定深度; 以及通过用形成有衬垫层的第一组沟槽填充第二绝缘层来形成第二隔离层。

公开(公告)号：US07427564B2

公开(公告)日：2008-09-23

申请号：US11418720

申请日：2006-05-05

Applicant: Chang-Youn Hwang ,  Hyung-Hwan Kim ,  Ik-Soo Choi ,  Hae-Jung Lee

Inventor： Chang-Youn Hwang ,  Hyung-Hwan Kim ,  Ik-Soo Choi ,  Hae-Jung Lee

IPC: H01L21/44

CPC classification number: H01L21/76897 ,  H01L21/76804 ,  H01L21/76831 ,  H01L27/10855

Abstract: A method for forming a storage node contact plug in a semiconductor device is provided. The method includes: forming an inter-layer insulation layer over a substrate having a conductive plug; etching a portion of the inter-layer insulation layer using at least line type storage node contact masks as an etch mask to form a first contact hole with sloping sidewalls; etching another portion of the inter-layer insulation layer underneath the first contact hole to form a second contact hole exposing the conductive plug, the second contact hole having substantially vertical sidewalls; and filling the first and second storage node contact holes to form a storage node contact plug.

Abstract translation: 提供一种在半导体器件中形成存储节点接触插头的方法。 该方法包括：在具有导电插塞的基板上形成层间绝缘层; 使用至少线型存储节点接触掩模作为蚀刻掩模蚀刻层间绝缘层的一部分，以形成具有倾斜侧壁的第一接触孔; 蚀刻在第一接触孔下面的层间绝缘层的另一部分，以形成露出导电插塞的第二接触孔，第二接触孔具有基本垂直的侧壁; 以及填充所述第一和第二存储节点接触孔以形成存储节点接触插头。

公开(公告)号：US08697525B2

公开(公告)日：2014-04-15

申请号：US13101424

申请日：2011-05-05

Applicant: Hyung-Hwan Kim ,  Seong-Su Lim ,  Sung-Eun Park ,  Seung-Seok Pyo ,  Min-Cheol Kang

Inventor： Hyung-Hwan Kim ,  Seong-Su Lim ,  Sung-Eun Park ,  Seung-Seok Pyo ,  Min-Cheol Kang

IPC: H01L21/336

CPC classification number: H01L29/0649 ,  H01L21/7682 ,  H01L21/76897 ,  H01L23/5222 ,  H01L23/53295 ,  H01L27/10855 ,  H01L27/10885 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device includes a plurality of first conductive patterns separated by a damascene pattern, a second conductive pattern buried in the damascene pattern, and a spacer including an air gap between the second conductive pattern and the first conductive patterns.

Abstract translation: 半导体器件包括由镶嵌图案分隔开的多个第一导电图案，埋在镶嵌图案中的第二导电图案，以及在第二导电图案和第一导电图案之间包括气隙的间隔件。

公开(公告)号：US08198171B2

公开(公告)日：2012-06-12

申请号：US12640118

申请日：2009-12-17

Applicant: Hyung-Hwan Kim

Inventor： Hyung-Hwan Kim

IPC: H01L21/76

CPC classification number: H01L21/76229 ,  H01L27/11546

Abstract: A method for fabricating a semiconductor device includes: providing a substrate; forming a plurality of trenches by etching the substrate; forming a first isolation layer by filling the plurality of the trenches with a first insulation layer; recessing the first insulation layer filling a first group of the plurality of the trenches to a predetermined depth; forming a liner layer over the first group of the trenches with the first insulation layer recessed to the predetermined depth; and forming a second isolation layer by filling the first group of the trenches, where the liner layer is formed, with a second insulation layer.

Abstract translation: 一种制造半导体器件的方法包括：提供衬底; 通过蚀刻所述衬底形成多个沟槽; 通过用第一绝缘层填充多个沟槽来形成第一隔离层; 使第一绝缘层将所述多个沟槽中的第一组填充到预定深度; 在所述第一组沟槽上形成衬里层，其中所述第一绝缘层凹入所述预定深度; 以及通过用形成有衬垫层的第一组沟槽填充第二绝缘层来形成第二隔离层。

公开(公告)号：US07229904B2

公开(公告)日：2007-06-12

申请号：US10876590

申请日：2004-06-28

Applicant: Hyung-Hwan Kim

Inventor： Hyung-Hwan Kim

IPC: H01L21/3205 ,  H01L21/4763 ,  H01L21/20 ,  H01L21/336 ,  H01L21/8242

CPC classification number: H01L21/76897

Abstract: Disclosed is a method for forming landing plug contacts in a semiconductor device. The method includes the steps of: forming a plurality of gate structures on a substrate, each gate structure including a gate hard mask; forming an inter-layer insulation layer on the gate structures; planarizing the inter-layer insulation layer through a chemical mechanical polishing (CMP) process until the gate hard mask is exposed; forming a hard mask material on the planarized inter-layer insulation layer; patterning the hard mask material, thereby forming a hard mask; forming a plurality of contact holes exposing the substrate disposed between the gate structures by etching the planarized inter-layer insulation layer with use of the hard mask as an etch mask; forming a polysilicon layer on the contact holes; and forming the landing plug contacts buried into the contact holes through a planarization process performed to the polysilicon layer until the gate hard mask is exposed.

Abstract translation: 公开了一种在半导体器件中形成着地插头触点的方法。 该方法包括以下步骤：在衬底上形成多个栅极结构，每个栅极结构包括栅极硬掩模; 在栅极结构上形成层间绝缘层; 通过化学机械抛光（CMP）工艺对层间绝缘层进行平坦化，直到栅极硬掩模露出; 在平坦化的层间绝缘层上形成硬掩模材料; 图案化硬掩模材料，从而形成硬掩模; 通过使用硬掩模作为蚀刻掩模蚀刻平坦化的层间绝缘层，形成暴露通过栅极结构之间设置的衬底的多个接触孔; 在所述接触孔上形成多晶硅层; 以及通过对所述多晶硅层进行的平坦化处理形成所述着陆栓接触件，所述接地孔接触件埋入所述接触孔中，直到所述栅极硬掩模露出为止。