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    Differentiation regulating agent containing gene which regulating differentiation from stem cells into natural killer cells as effective ingredient
    3.
    发明申请
    Differentiation regulating agent containing gene which regulating differentiation from stem cells into natural killer cells as effective ingredient 审中-公开
    分化调节剂含有调节干细胞分化为天然杀伤细胞作为有效成分的基因

    公开(公告)号：US20070042344A1

    公开(公告)日：2007-02-22

    申请号：US10597305

    申请日：2005-01-20

    申请人： Inpyo Choi ,  Hyung-Sik Kang ,  Suk-Ran Yoon ,  Eun-Mi Kim

    发明人： Inpyo Choi ,  Hyung-Sik Kang ,  Suk-Ran Yoon ,  Eun-Mi Kim

    IPC分类号： C12Q1/00 ,  C12Q1/68 ,  C12N5/08

    CPC分类号： C07K14/47 ,  A61K38/00 ,  C07K14/4702 ,  C12N5/0646 ,  C12Q1/6886 ,  C12Q2600/158

    摘要： The present invention relates to a cell differentiation regulating agent containing a gene regulating differentiation from stem cells into natural killer cells as an effective ingredient, more precisely, a cell differentiation regulating agent containing a gene regulating differentiation from stem cells into premature natural killer cells as an effective ingredient and a screening method of the gene by taking advantage of SAGE. The gene of the present invention is a novel one that is confirmed not to be like any other known genes regulating differentiation from stem cells into natural killer cells. Though, the gene can be easily screened by SAGE and a natural killer cell differentiation-regulating agent containing the gene as an effective ingredient can be effectively used as an anticancer agent.

    摘要翻译： 本发明涉及含有调节从干细胞分化为天然杀伤细胞作为有效成分的基因的细胞分化调节剂，更确切地说，涉及含有调节从干细胞分化为过早天然杀伤细胞的基因的细胞分化调节剂 有效成分和利用SAGE的基因筛选方法。 本发明的基因是一种新的，被证明不像调节从干细胞分化为天然杀伤细胞的任何其它已知的基因。 虽然该基因可以容易地被SAGE筛选，并且含有该基因作为有效成分的天然杀伤细胞分化调节剂可以有效地用作抗癌剂。

    Method for fabricating recess gate in semiconductor device
    5.
    发明授权
    Method for fabricating recess gate in semiconductor device 有权
    在半导体器件中制造凹槽的方法

    公开(公告)号：US07838361B2

    公开(公告)日：2010-11-23

    申请号：US12239492

    申请日：2008-09-26

    申请人： Yong-Tae Cho ,  Eun-Mi Kim

    发明人： Yong-Tae Cho ,  Eun-Mi Kim

    IPC分类号： H01L21/336

    CPC分类号： H01L21/28114 ,  H01L29/4236 ,  H01L29/42372 ,  H01L29/66621

    摘要： A method for fabricating a recess gate in a semiconductor device includes etching a silicon substrate to form a trench that defines an active region, forming a device isolation layer that gap-fills the trench, forming a hard mask layer over the silicon substrate, the hard mask layer comprising a stack of an oxide layer and an amorphous carbon layer, wherein the hard mask layer exposes a channel target region of the active region, and forming a recess region with a dual profile by first etching and second etching the channel target region using the hard mask layer as an etch barrier, wherein the second etching is performed after removing the amorphous carbon layer.

    摘要翻译： 一种在半导体器件中制造凹陷栅的方法，包括蚀刻硅衬底以形成限定有源区的沟槽，形成间隙填充沟槽的器件隔离层，在硅衬底上形成硬掩模层，硬的 掩模层，其包括氧化物层和非晶碳层的堆叠，其中所述硬掩模层暴露所述有源区的沟道目标区域，并且通过第一蚀刻形成具有双轮廓的凹陷区域，并且使用 所述硬掩模层作为蚀刻阻挡层，其中所述第二蚀刻在去除所述无定形碳层之后进行。

    Method of fabricating recess gate in semiconductor device
    6.
    发明授权
    Method of fabricating recess gate in semiconductor device 有权
    在半导体器件中制造凹槽的方法

    公开(公告)号：US07642161B2

    公开(公告)日：2010-01-05

    申请号：US11644880

    申请日：2006-12-26

    申请人： Yong-Tae Cho ,  Eun-Mi Kim

    发明人： Yong-Tae Cho ,  Eun-Mi Kim

    IPC分类号： H01L21/336

    CPC分类号： H01L29/66621

    摘要： A method of fabricating a semiconductor device includes forming an isolation structure in a substrate to define an active region, forming a recess mask pattern over the isolation structure and the active region, etching the isolation structure exposed by the recess mask pattern to a certain depth, etching the substrate to form a recess pattern, and forming a gate electrode over the recess pattern.

    摘要翻译： 制造半导体器件的方法包括在衬底中形成隔离结构以限定有源区，在隔离结构和有源区上形成凹陷掩模图案，将由凹槽掩模图案暴露的隔离结构蚀刻到一定深度， 蚀刻衬底以形成凹陷图案，并在凹槽图案上形成栅电极。

    Semiconductor device and method of fabricating the same
    8.
    发明授权
    Semiconductor device and method of fabricating the same 有权
    半导体装置及其制造方法

    公开(公告)号：US08003485B2

    公开(公告)日：2011-08-23

    申请号：US12318466

    申请日：2008-12-30

    申请人： Yong-Tae Cho ,  Hae-Jung Lee ,  Eun-Mi Kim ,  Kyeong-Hyo Lee

    发明人： Yong-Tae Cho ,  Hae-Jung Lee ,  Eun-Mi Kim ,  Kyeong-Hyo Lee

    IPC分类号： H01L29/78 ,  H01L21/762

    CPC分类号： H01L29/66795 ,  H01L29/7851

    摘要： In a semiconductor device and related method of fabricating the same, a hard mask layer is formed over a substrate, portions of the hard mask layer and the substrate are etched to form trenches having protruding portions at sidewalls, and an insulation layer buried in the trenches is formed to form device isolation regions having protruding portions at sidewalls, wherein the device isolation regions decrease a portion of a width of active regions.

    摘要翻译： 在制造半导体器件及其相关方法中，在衬底上形成硬掩模层，硬掩模层和衬底的部分被蚀刻以形成在侧壁具有突出部分的沟槽，并且埋在沟槽中的绝缘层 被形成以形成在侧壁具有突出部分的器件隔离区域，其中器件隔离区域减小有效区域宽度的一部分。

    Method for fabricating semiconductor device having taper type trench
    9.
    发明授权
    Method for fabricating semiconductor device having taper type trench 失效
    制造具有锥形沟槽的半导体器件的方法

    公开(公告)号：US07553767B2

    公开(公告)日：2009-06-30

    申请号：US11455847

    申请日：2006-06-20

    申请人： Yong-Tae Cho ,  Eun-Mi Kim

    发明人： Yong-Tae Cho ,  Eun-Mi Kim

    IPC分类号： H01L21/302 ,  H01L21/461

    CPC分类号： H01L21/76232

    摘要： A method for fabricating a semiconductor includes: etching a substrate to a predetermined depth to form an upper trench with taper edges; etching the substrate beneath the upper trench to form a lower trench with approximately vertical edges; forming a device isolation layer disposed within the upper and lower trenches; and etching an active region of the substrate defined by the upper and lower trenches to a predetermined depth to form a recess pattern for a gate.

    摘要翻译： 一种制造半导体的方法包括：将衬底蚀刻到预定深度以形成具有锥形边缘的上沟槽; 蚀刻在上沟槽下方的衬底以形成具有大致垂直边缘的下沟槽; 形成设置在所述上​​沟槽和下沟槽内的器件隔离层; 并且将由所述上沟槽和下沟槽限定的衬底的有源区域蚀刻到预定深度以形成用于栅极的凹陷图案。