公开(公告)号：US3629667A

公开(公告)日：1971-12-21

申请号：US3629667D

申请日：1969-03-14

Applicant: IBM

Inventor： LUBART NEIL D ,  VORA MADHUKAR B

IPC: H01L29/8605 ,  H01L5/02

CPC classification number: H01L29/8605

Abstract: A diffused resistor for semiconductor integrated circuits which avoids the problems caused by the high surface current density. The resistor includes at least one semiconductor region of conductivity type opposite to the resistor proper located between a pair of ohmic contacts to the resistor region. This semiconductor region diverts the current flow from the surface of the resistor region and causes a more uniform current distribution across the surface of the ohmic contacts.

公开(公告)号：US3703420A

公开(公告)日：1972-11-21

申请号：US3703420D

申请日：1970-03-03

Applicant: IBM

Inventor： VORA MADHUKAR B

IPC: H01L21/00 ,  H01L21/22 ,  H01L21/225 ,  H01L27/00 ,  H01L29/06 ,  H01L29/73 ,  H01L7/36 ,  C23C13/00 ,  H01L5/00

CPC classification number: H01L29/06 ,  H01L21/00 ,  H01L21/22 ,  H01L21/225 ,  H01L27/00 ,  H01L29/73 ,  Y10S148/037 ,  Y10S148/053 ,  Y10S148/085 ,  Y10S148/096 ,  Y10S148/122 ,  Y10S148/167 ,  Y10S438/969

Abstract: A NOVEL TRANSISTOR WHEREIN CURRENT TRAVELS LATERALLY ALONG THE SEMI-CONDUCTOR SURFACE HAVING POLYCRYSTALLINE DIFFUSION PATHS IN ITS SURFACE WHICH SERVE AS THE MEANS OF INTRODUCING IMPURITIES IN A VERTICAL ORIENTATION INTO SURROUNDING SINGLE CRYSTAL MATERIAL BECAUSE OF THE MORE RAPID DIFFUSION RATE OF POLYCRYSTALLINE MATERIAL. APPROPRAITE COLLECTOR/EMITTER AND BASE CONTACTS ARE MADE THERETO. PROCESS FOR FORMING SUCH A LATERAL SEMI-CONDUCTOR BY DIFFUSING THROUGH A POLYCRYSTALLINE DIFFUSION PATH OR CHANNEL, DIFFUSION RAPIDLY TAKING PLACE IN A LATERAL DIRECTION

THROUGH THE POLYCRYSTALLINE SILICON WHICH IS IN AN EPITAXIAL LAYER. IN AN ALTENATE EMBODIMENT, DIFFUSION IS THROUGH MONOCRYSTALLINE AREAS TO AN ULTRA HIGHLY DOPED SUBSTRATE AREA.

公开(公告)号：US3621346A

公开(公告)日：1971-11-16

申请号：US3621346D

申请日：1970-01-28

Applicant: IBM

Inventor： CHANG JOSEPH J ,  VORA MADHUKAR B

IPC: H01L21/763 ,  H01L21/00 ,  H01L21/205 ,  H01L21/331 ,  H01L21/74 ,  H01L23/535 ,  H01L27/00 ,  H01L29/73 ,  H01L11/00

CPC classification number: H01L21/00 ,  H01L21/743 ,  H01L23/535 ,  H01L27/00 ,  H01L2924/0002 ,  Y10S148/085 ,  Y10S148/115 ,  Y10S148/122 ,  Y10S148/145 ,  H01L2924/00

Abstract: A process wherein epitaxial silicon is grown on a substrate of single-crystal silicon with islands of silicon dioxide thereon, whereby single crystal epitaxial material is grown over the single-crystal substrate areas, but polycrystalline silicon is grown over the silicon dioxide islands. Since impurity diffusion occurs more rapidly through polycrystalline material than through single-crystalline material diffusion schemes can be obtained using the rapid diffusion pathway provided by the polycrystalline material to provide subsurface configurations which are completely enclosed by single-crystal material, for instance, a buried subcollector can be formed by growing polycrystalline silicon material horizontally, extending a narrow polycrystalline channel upward to the device surface, and subsequently diffusing impurities down through the narrow vertical polycrystalline channel into the lateral polycrystalline subcollector. Further, an electrical underpass can be formed which has a very low resistance by again using the rapid diffusion characteristics of polycrystalline silicon to grow polycrystalline silicon of the desired shape which can be rapidly diffused to provide, in comparison to background, a high conductivity path. By control of the substrate crystalline orientation, polycrystalline material can be grown which terminates because of sidewall convergence. This is desirable where it is required to terminate polycrystalline growth and begin single-crystal growth without any alteration in process conditions. The devices described are also claimed.

公开(公告)号：US3607468A

公开(公告)日：1971-09-21

申请号：US3607468D

申请日：1968-10-07

Applicant: IBM

Inventor： CHANG JOSEPH J F ,  VORA MADHUKAR B

IPC: A47L15/42 ,  G01D5/244 ,  H01L21/00 ,  H01L21/22 ,  H01L21/265 ,  H01L21/331 ,  H01L27/00 ,  H01L29/36 ,  H01L29/73 ,  H01L7/44

CPC classification number: H01L29/36 ,  A47L15/42 ,  G01D5/244 ,  H01L21/00 ,  H01L21/22 ,  H01L21/265 ,  H01L27/00 ,  H01L29/73 ,  Y10S148/037 ,  Y10S148/04 ,  Y10S148/085 ,  Y10S148/151 ,  Y10S148/157

Abstract: A method for making a high-performance NPN silicon semiconductor device which has an arsenic emitter which gives a substantial improvement in transistor speed and current gain over similar phosphorous emitters. Arsenic atoms in the emitter region tend to squeeze the P-type impurity, such as boron in the base into a narrow base layer. For the same integrated base doping, a much narrower base can be obtained with arsenic-doped emitters than with phosphorous-doped emitters.